基于FPGA的UDP/IP硬件协议栈的研究与实现
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摘要
以视频、音频等大数据量为特点的以太网应用成为嵌入式以太网技术广泛普及的因素之一。针对此类应用,采用UDP作为传输协议能有效解决传输速度的问题。目前业内已有的嵌入式以太网解决方案众多,其中在微控制器内移植软件TCP/IP协议栈的解决方案会受制于微控制器的ROM空间大小;而ASIC解决方案则受制于成本因素,且内置的协议栈不可更改。这些因素均不利于嵌入式以太网高速传输应用的推广。
针对这些问题,本文提出UDP/IP协议栈硬件实现方法,即协议栈的处理功能采用硬件描述语言重新编写,并在FPGA上实现以太网传输的功能。本文首先分析了UDP/IP协议栈的各层协议功能,然后针对应用和硬件的特点设计出精简的UDP/IP硬件协议栈,并对协议栈子模块进行了功能验证。该协议栈采用了模块化设计的思想,按照功能划分并逐一实现各协议模块,紧接着由顶层模块统一控制,为PHY芯片和应用层程序提供符合标准的接口,使得该协议栈模块能完成基本的网络数据传输功能。
本文的创新点在于提出UDP/IP硬件协议栈内置于FPGA以实现嵌入式以太网传输的方案,并对该协议栈的功能进行了研究和实现。仿真实验结果表明,各协议模块功能均达到预期的效果。但要将现有研究成果投入到网络应用中,仍需要进行更深入的研究。
There are more and more Ethernet applications with a large amount of data, such as high-definition video and high-definition audio, this makes the embedded Ethernet technology become more popular. For this type of data transmission, it is common to use UDP as transfer protocol to meet the application demands in the industry. For the present, there are a number of embedded Ethernet solutions, among which the solutions with the UDP/IP software stack in the micro-controller are subject to the micro-controller ROM space. While the solutions with ASIC are subject to the cost factors and unchangeable protocol stack. All of these factors do not benefit the popularization of the embedded Ethernet applications.
For these problems above, the thought of bringing the UDP/IP hardware stack into FPGA is proposed, namely, the function of the UDP/IP stack is re-described with hardware language, and then is implemented in FPGA. First of all, the functions of UDP/IP stack in different layers are analyzed in detail. Then a simplified UDP/IP hardware stack is designed for applications and hardware. Finally, the modules for different protocols are tested and verified. With the modular design idea, sub-modules are implemented respectively according to a streamlined UDP/IP stack, and then controlled by the top-level module, providing standard interfaces for PHY chip and top-level applications, so that the UDP/IP hardware stack can process network data.
The innovation of this paper is to propose UDP/IP hardware stack in FPGA and do the research and realization of functions of the stack. Simulation results show that the stack module functions have achieved the desired results. However, with the existing research results applied to the network applications, there are still more studies required in-depth.
针对这些问题,本文提出UDP/IP协议栈硬件实现方法,即协议栈的处理功能采用硬件描述语言重新编写,并在FPGA上实现以太网传输的功能。本文首先分析了UDP/IP协议栈的各层协议功能,然后针对应用和硬件的特点设计出精简的UDP/IP硬件协议栈,并对协议栈子模块进行了功能验证。该协议栈采用了模块化设计的思想,按照功能划分并逐一实现各协议模块,紧接着由顶层模块统一控制,为PHY芯片和应用层程序提供符合标准的接口,使得该协议栈模块能完成基本的网络数据传输功能。
本文的创新点在于提出UDP/IP硬件协议栈内置于FPGA以实现嵌入式以太网传输的方案,并对该协议栈的功能进行了研究和实现。仿真实验结果表明,各协议模块功能均达到预期的效果。但要将现有研究成果投入到网络应用中,仍需要进行更深入的研究。
There are more and more Ethernet applications with a large amount of data, such as high-definition video and high-definition audio, this makes the embedded Ethernet technology become more popular. For this type of data transmission, it is common to use UDP as transfer protocol to meet the application demands in the industry. For the present, there are a number of embedded Ethernet solutions, among which the solutions with the UDP/IP software stack in the micro-controller are subject to the micro-controller ROM space. While the solutions with ASIC are subject to the cost factors and unchangeable protocol stack. All of these factors do not benefit the popularization of the embedded Ethernet applications.
For these problems above, the thought of bringing the UDP/IP hardware stack into FPGA is proposed, namely, the function of the UDP/IP stack is re-described with hardware language, and then is implemented in FPGA. First of all, the functions of UDP/IP stack in different layers are analyzed in detail. Then a simplified UDP/IP hardware stack is designed for applications and hardware. Finally, the modules for different protocols are tested and verified. With the modular design idea, sub-modules are implemented respectively according to a streamlined UDP/IP stack, and then controlled by the top-level module, providing standard interfaces for PHY chip and top-level applications, so that the UDP/IP hardware stack can process network data.
The innovation of this paper is to propose UDP/IP hardware stack in FPGA and do the research and realization of functions of the stack. Simulation results show that the stack module functions have achieved the desired results. However, with the existing research results applied to the network applications, there are still more studies required in-depth.
引文
[1]田波.地球将拥有电子皮肤.国外科技动态,2000,(2).19-20
[2]王洁.一种新型全网资源监管系统的研究与实现.微计算机信息,2007,23(27).88-90
[3]彭蔓蔓.嵌入式系统导论[M].北京:人民邮电出版社,2008
[4]桑楠.嵌入式系统原理及应用开发技术.北京:高等教育出版社,2008
[5] Weidong Lu. Designing TCP/IP Functions In FPGAs. MSc Thesis, Code number CE-MS-2003.09
[6] Christophoros Kachris. Design and Implementation of a TCP/IP core for reconfigureable logic. Crete: Technical University of Crete Electronic and Computer Engineering Department, 2001
[7] Hynix semiconductor. Datasheet HMS91C7432. www.hynix.com
[8] Seiko Instruments Inc. Hardware specification S-7600A TCP/IP Network Stack LSI -Revision 1.3
[9] K Morita, K Abe, Implementation of UDP/IP Protocol on FPGA and Its Performance Evaluation. IPSJ General Conf. Special5, 157-158
[10] A L?fgren, L Lodesten, S Sjoholm. An analysis of FPGA-based UDP/IP stack parallelism for embedded ethernet connectivity. NORCHIP Conference, 2005, 23rd
[11] H. Fallside, M. John, and S. Smith. Internet Connected FPGAs, IEEE Symposium on Field-Programmable Custom Computing Machines, April 2000, 289-290
[12] Xilinx. Virtex-5 Datasheet. www.xilinx.com
[13] Altera. CYCLONE II FPGA Datasheet. www.altera.com
[14]张大波.嵌入式系统原理、设计与应用.北京:机械工业出版社,2005
[15]周立功.SOPC嵌入式系统基础教程.北京:北京航天航空大学出版社,2006
[16] EDA先锋工作室、王诚等著.Altera FPGA/CPLD设计(基础篇).北京:人民邮电出版社,2005.1-73
[17]刘皖、何道君、谭明著.FPGA系统设计与实践.北京:清华大学出版社,2006.1-132
[18]潘松、黄继业.EDA技术与VHDL.北京:清华大学出版社,2005
[19] Wiznet. W3150 Datasheet. www.wiznet.com
[20] IETF组织. IPv4. http://zh.wikipedia.org/wiki/IPv4
[21]陈亮.移动IPv6的研究与应用.福州:福建电脑,2009,(11).38-39
[22] W.Richard Stevens著.范建华、胥光辉、张涛等译.TCP/IP详解1,协议.北京:机械工业出版社,2000
[23]诺尔加德、马洪兵、谷源涛.嵌入式系统硬件与软件架构.北京:人民邮电出版社,2008
[24] IETF组织.RFC768 User Datagram Protocol
[25] IETF组织.RFC791 Internet Protocol
[26] IETF组织.RFC792 Internet Control Message Protocol
[27] IETF组织.RFC793 Transmission Control Protocol
[28] IETF组织.RFC826 Ethernet Address Resolution Protocol
[29]徐洪波、俞承芳.基于FPGA的以太网MAC子层协议设计实现.复旦大学学报(自然科学版),2004,40(3).50-53
[30] IEEE组织. IEEE 802.3. 2005
[31]徐敏、孙恺、潘峰.开源软核处理器OPENRISC的SOPC设计.北京:北京航空航天大学出版社,2008.175-210
[32]夏泽中、柴庆芬.循环冗余校验码算法的分析及VHDL语言实现[J].计算机与数字工程,2005,31(3).104-106
[33]宋富新,朱晓明,马小社.CRC编码的并行算法与软件实现.西安:电子科技,2007.11.62-65
[2]王洁.一种新型全网资源监管系统的研究与实现.微计算机信息,2007,23(27).88-90
[3]彭蔓蔓.嵌入式系统导论[M].北京:人民邮电出版社,2008
[4]桑楠.嵌入式系统原理及应用开发技术.北京:高等教育出版社,2008
[5] Weidong Lu. Designing TCP/IP Functions In FPGAs. MSc Thesis, Code number CE-MS-2003.09
[6] Christophoros Kachris. Design and Implementation of a TCP/IP core for reconfigureable logic. Crete: Technical University of Crete Electronic and Computer Engineering Department, 2001
[7] Hynix semiconductor. Datasheet HMS91C7432. www.hynix.com
[8] Seiko Instruments Inc. Hardware specification S-7600A TCP/IP Network Stack LSI -Revision 1.3
[9] K Morita, K Abe, Implementation of UDP/IP Protocol on FPGA and Its Performance Evaluation. IPSJ General Conf. Special5, 157-158
[10] A L?fgren, L Lodesten, S Sjoholm. An analysis of FPGA-based UDP/IP stack parallelism for embedded ethernet connectivity. NORCHIP Conference, 2005, 23rd
[11] H. Fallside, M. John, and S. Smith. Internet Connected FPGAs, IEEE Symposium on Field-Programmable Custom Computing Machines, April 2000, 289-290
[12] Xilinx. Virtex-5 Datasheet. www.xilinx.com
[13] Altera. CYCLONE II FPGA Datasheet. www.altera.com
[14]张大波.嵌入式系统原理、设计与应用.北京:机械工业出版社,2005
[15]周立功.SOPC嵌入式系统基础教程.北京:北京航天航空大学出版社,2006
[16] EDA先锋工作室、王诚等著.Altera FPGA/CPLD设计(基础篇).北京:人民邮电出版社,2005.1-73
[17]刘皖、何道君、谭明著.FPGA系统设计与实践.北京:清华大学出版社,2006.1-132
[18]潘松、黄继业.EDA技术与VHDL.北京:清华大学出版社,2005
[19] Wiznet. W3150 Datasheet. www.wiznet.com
[20] IETF组织. IPv4. http://zh.wikipedia.org/wiki/IPv4
[21]陈亮.移动IPv6的研究与应用.福州:福建电脑,2009,(11).38-39
[22] W.Richard Stevens著.范建华、胥光辉、张涛等译.TCP/IP详解1,协议.北京:机械工业出版社,2000
[23]诺尔加德、马洪兵、谷源涛.嵌入式系统硬件与软件架构.北京:人民邮电出版社,2008
[24] IETF组织.RFC768 User Datagram Protocol
[25] IETF组织.RFC791 Internet Protocol
[26] IETF组织.RFC792 Internet Control Message Protocol
[27] IETF组织.RFC793 Transmission Control Protocol
[28] IETF组织.RFC826 Ethernet Address Resolution Protocol
[29]徐洪波、俞承芳.基于FPGA的以太网MAC子层协议设计实现.复旦大学学报(自然科学版),2004,40(3).50-53
[30] IEEE组织. IEEE 802.3. 2005
[31]徐敏、孙恺、潘峰.开源软核处理器OPENRISC的SOPC设计.北京:北京航空航天大学出版社,2008.175-210
[32]夏泽中、柴庆芬.循环冗余校验码算法的分析及VHDL语言实现[J].计算机与数字工程,2005,31(3).104-106
[33]宋富新,朱晓明,马小社.CRC编码的并行算法与软件实现.西安:电子科技,2007.11.62-65