基于并行自适应有限元的互连线建模与分析方法
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摘要
从集成电路的诞生到现在的短短半个多世纪,快速发展的集成电路技术,为电子信息科学发展注入了新的活力,推动了计算机、通信、消费类电子、移动互联网产业的蓬勃发展。集成电路的工艺和集成电路设计方法学的不断进步,促进集成电路的高速发展。一方面,随着集成电路器件特征尺寸按比例缩小到纳米尺度,电路工作频率达到GHz,互连线寄生效应带来的互连线串扰、IR-drop、延迟、噪声等越来越严重,互连线成为影响集成电路性能和可靠性的关键因素。因此,集成电路设计方法学经历了从以器件为中心的设计转变到以互连线为中心的设计的变革,寄生参数提取成为以互连线为中心的第二代集成电路设计方法学的核心科学问题。另一方面,持续的工艺技术的进步驱动了集成电路不断的微小型化,但是随着一些工艺技术开始达到物理极限,器件特征尺寸的进一步缩小将会导致技术和成本两方面面临越来越大的挑战,三维芯片(Three dimensional integrated circuit,3D IC)成为继续驱动集成电路沿着摩尔定律道路不断前进最有希望的技术。三维集成电路是一种系统级构架新方法,它通过硅通孔(Through-silicon via,TSV)垂直互连实现多平面芯片的层叠。相比与二维平面芯片,三维芯片能够提高芯片器件密度、减小信号延迟、降低芯片功耗,同时通过TSV垂直互连实现的三维芯片同质集成或异质集成,能比传统系统集成芯片(SoC)能够提供更好的性能。虽然三维芯片能够带来电性能方面的巨大收益,然而严重的散热问题极大影响三维芯片的性能和可靠性。
基于以上两方面因素,本文集中研究集成电路互连线建模与分析方法,包括大规模复杂结构集互连线寄生电容参数提取算法研究和多TSV垂直互连结构的三维芯片热分析方法的研究。本论文针对从版图提取、初始网格生成到全自动的寄生参数提取与三维芯片热分析等各个步骤展开了研究。
互连线参数提取广泛应用于构造互连线等效电路模型,是超大规模集成电路设计的关键技术之一；三维芯片热分析是三维芯片设计面临的首要挑战,为EDA领域的热点研究领域之一。集成电路庞大的、复杂的互连线结构以及几百上千的TSV垂直互连线结构分别对寄生参数提取和三维芯片热分析都带来了计算复杂度的瓶颈问题。本论文首次将并行自适应有限元(Adaptive finite element method, AFEM)应用于集成电路互连线建模与分析方法的研究,主要包括并行自适应有限元互连线电容提取算法(ParAFEMCap)和并行自适应有限元三维芯片稳态热分析方法(ParAFEMThermo).本文提出的ParAFEMCap和ParAFEMThermo算法具有很高的并行扩展性和数值精度。首先,通过采用一些先进的并行技术,比如并行网格加密和动态负载平衡技术,本文提出的ParAFEMCap和ParAFEMThermo算法具有很高的并行扩展性。目前已知,ParAFEMCap是第一个能并行运行在成百上千CPU核上的电容提取的场求解器。其次,本文提出的ParAFEMCap和ParAFEMThermo算法基于自适应有限元(Adaptive FEM),能够以理论可证的最优收敛的方式收敛到问题的精确解。通过改变后验误差估计子的阂值,ParAFEMCap和ParAFEMThermo解的精度能够很容易的得到控制,同时通过增加CPU核的数目,ParAFEMCap和ParAFEMThermo运行时间能够迅速的减小。再次,本文提出的ParAFEMCap算法具有线性复杂度,使得ParAFEMCap对于大规模互连线电容提取具有非常大的优势,同时ParAFEMThermo也是具有强大计算能力的高性能三维芯片热分析工具。
本文采用完整的数值实验验证了以上方法的高计算效率,高精确性和高并行可扩展性。
From the birth of the first integrated circuit (IC) chip to nowadays, rapid development of integrated circuit technology has injected vast vitality to electronic information industry and promoted the flourish of computer, communications, consumer electronics and mobile internet industries in just a half century. As the integrated circuit manufacture process and IC design methodology advance, integrated circuits have been continuously upgraded. On the one hand, as the VLSI thechnology scales to nanoscale and the circuit frequency reaches gigahertz, interconnect cross-talk, IR-drop, signal delay and noise induced by the parasitic interconnect effect become more and more serious.The interconnects of integrated circuits become the key effect which affects the performance and reliability of the circuits. Therefore, the IC design methodology has experienced the revolution from the device-centric design to interconnect-centric design, and the parasitic extraction of interconnects has been the key issue in the second generation interconnect-centric IC design methodology. On the other hand, the continuous advance of manufacture process enables the miniaturization of the integrated circuits, but some manufacture processes have reached their physical limits, such that further scaling down of the technology size will result in more and more challenges in the cost and the manufacture process. Three-dimensional integrated circuit (3D IC) is a system-level architecture which implements chip stacking by using Through-silicon via (TSV) as vertical interconnections. Compared to2D ICs,3D ICs can get smaller footprint size, higher density of the devices and reduce the signal delay and the power. At the same time,3D-IC can implement homogeneous integration or heterogeneous integration by TSV.3D-IC is a promising technology to extend the Moore's Law. Though3D IC can bring on huge improvement in IC's electrical performance, serious thermal issue becomes the major challenge in the performance and reliability of3D IC.
Considering the above significant issues, modeling and analysis methods for interconnect of integrated circuits has been proposed in this paper, including parasitic capacitance extraction of large scale and complex structure interconnect in integrated circuits and thermal analysis of3D IC with TSV vertical interconnections. In this paper, comprehensive research on layout extraction, mesh generation to fully automatic parasitic extraction of interconnects and fully automatic thermal analysis of3D IC has been conducted.
Parasitic extraction is one of key techniques in very scale integrated circuit design that has been widely used to build the equivalent-circuit model of interconnects; thermal has been the major challenge in3D IC design and it is one of important research issues in EDA. Large-scale interconnects with complex multilayer structures and vertical interconnects with hundreds of TSVs bring on huge computational bottleneck of parasitic extraction and3D IC thermal analysis respectively. In this paper, a parallel adaptive finite element method is first applied to modeling and analysis method for interconnects of integrated circuits, including a parallel adaptive finite element method for capacitance extraction of large scale interconnects (ParAFEMCap) and a parallel adaptive finite element method for steady thermal analysis of3D IC (ParAFEMThermo). The proposed modeling and analysis method for interconnects can provide extremely high parallel scalability and numerical accuracy. First, the proposed ParAFEMCap and ParAFEMThermo have the potential of high parallel scalability by taking advantages of several advanced parallel techniques, such as parallel adaptive mesh refinement and dynamic load balancing. To the best of authors'knowledge, this is the first capacitance extraction and thermal analysis field solver that is able to run in parallel on hundreds of and even thousands of CPU cores. Second, based on the adaptive finite element method, the proposed ParAFEMCap and ParAFEMThermo are proved to converge to the exact solution of the electromagnetic problems and heat diffusion problem in a theoretically quasi-optimal rate. The solution precision of ParAFEMCap and ParAFEMThermo can easily be controlled by varying the threshold for the a posteriori error estimator, while the computational time can easily be reduced by increasing the number of CPU cores. Moreover, ParAFEMCap is shown to have the same linear computation complexity as those integral equation methods, which make it very promising for capacitance extraction of large-scale interconnect problems, while ParAFEMThermo also is an effective thermal analysis tool with high computational ability.
Numerical results will demonstrate that ParAFEMCap and ParAFEMThermo have the advantages of high computational efficiency, high accuracy and high parallel scalability.
基于以上两方面因素,本文集中研究集成电路互连线建模与分析方法,包括大规模复杂结构集互连线寄生电容参数提取算法研究和多TSV垂直互连结构的三维芯片热分析方法的研究。本论文针对从版图提取、初始网格生成到全自动的寄生参数提取与三维芯片热分析等各个步骤展开了研究。
互连线参数提取广泛应用于构造互连线等效电路模型,是超大规模集成电路设计的关键技术之一；三维芯片热分析是三维芯片设计面临的首要挑战,为EDA领域的热点研究领域之一。集成电路庞大的、复杂的互连线结构以及几百上千的TSV垂直互连线结构分别对寄生参数提取和三维芯片热分析都带来了计算复杂度的瓶颈问题。本论文首次将并行自适应有限元(Adaptive finite element method, AFEM)应用于集成电路互连线建模与分析方法的研究,主要包括并行自适应有限元互连线电容提取算法(ParAFEMCap)和并行自适应有限元三维芯片稳态热分析方法(ParAFEMThermo).本文提出的ParAFEMCap和ParAFEMThermo算法具有很高的并行扩展性和数值精度。首先,通过采用一些先进的并行技术,比如并行网格加密和动态负载平衡技术,本文提出的ParAFEMCap和ParAFEMThermo算法具有很高的并行扩展性。目前已知,ParAFEMCap是第一个能并行运行在成百上千CPU核上的电容提取的场求解器。其次,本文提出的ParAFEMCap和ParAFEMThermo算法基于自适应有限元(Adaptive FEM),能够以理论可证的最优收敛的方式收敛到问题的精确解。通过改变后验误差估计子的阂值,ParAFEMCap和ParAFEMThermo解的精度能够很容易的得到控制,同时通过增加CPU核的数目,ParAFEMCap和ParAFEMThermo运行时间能够迅速的减小。再次,本文提出的ParAFEMCap算法具有线性复杂度,使得ParAFEMCap对于大规模互连线电容提取具有非常大的优势,同时ParAFEMThermo也是具有强大计算能力的高性能三维芯片热分析工具。
本文采用完整的数值实验验证了以上方法的高计算效率,高精确性和高并行可扩展性。
From the birth of the first integrated circuit (IC) chip to nowadays, rapid development of integrated circuit technology has injected vast vitality to electronic information industry and promoted the flourish of computer, communications, consumer electronics and mobile internet industries in just a half century. As the integrated circuit manufacture process and IC design methodology advance, integrated circuits have been continuously upgraded. On the one hand, as the VLSI thechnology scales to nanoscale and the circuit frequency reaches gigahertz, interconnect cross-talk, IR-drop, signal delay and noise induced by the parasitic interconnect effect become more and more serious.The interconnects of integrated circuits become the key effect which affects the performance and reliability of the circuits. Therefore, the IC design methodology has experienced the revolution from the device-centric design to interconnect-centric design, and the parasitic extraction of interconnects has been the key issue in the second generation interconnect-centric IC design methodology. On the other hand, the continuous advance of manufacture process enables the miniaturization of the integrated circuits, but some manufacture processes have reached their physical limits, such that further scaling down of the technology size will result in more and more challenges in the cost and the manufacture process. Three-dimensional integrated circuit (3D IC) is a system-level architecture which implements chip stacking by using Through-silicon via (TSV) as vertical interconnections. Compared to2D ICs,3D ICs can get smaller footprint size, higher density of the devices and reduce the signal delay and the power. At the same time,3D-IC can implement homogeneous integration or heterogeneous integration by TSV.3D-IC is a promising technology to extend the Moore's Law. Though3D IC can bring on huge improvement in IC's electrical performance, serious thermal issue becomes the major challenge in the performance and reliability of3D IC.
Considering the above significant issues, modeling and analysis methods for interconnect of integrated circuits has been proposed in this paper, including parasitic capacitance extraction of large scale and complex structure interconnect in integrated circuits and thermal analysis of3D IC with TSV vertical interconnections. In this paper, comprehensive research on layout extraction, mesh generation to fully automatic parasitic extraction of interconnects and fully automatic thermal analysis of3D IC has been conducted.
Parasitic extraction is one of key techniques in very scale integrated circuit design that has been widely used to build the equivalent-circuit model of interconnects; thermal has been the major challenge in3D IC design and it is one of important research issues in EDA. Large-scale interconnects with complex multilayer structures and vertical interconnects with hundreds of TSVs bring on huge computational bottleneck of parasitic extraction and3D IC thermal analysis respectively. In this paper, a parallel adaptive finite element method is first applied to modeling and analysis method for interconnects of integrated circuits, including a parallel adaptive finite element method for capacitance extraction of large scale interconnects (ParAFEMCap) and a parallel adaptive finite element method for steady thermal analysis of3D IC (ParAFEMThermo). The proposed modeling and analysis method for interconnects can provide extremely high parallel scalability and numerical accuracy. First, the proposed ParAFEMCap and ParAFEMThermo have the potential of high parallel scalability by taking advantages of several advanced parallel techniques, such as parallel adaptive mesh refinement and dynamic load balancing. To the best of authors'knowledge, this is the first capacitance extraction and thermal analysis field solver that is able to run in parallel on hundreds of and even thousands of CPU cores. Second, based on the adaptive finite element method, the proposed ParAFEMCap and ParAFEMThermo are proved to converge to the exact solution of the electromagnetic problems and heat diffusion problem in a theoretically quasi-optimal rate. The solution precision of ParAFEMCap and ParAFEMThermo can easily be controlled by varying the threshold for the a posteriori error estimator, while the computational time can easily be reduced by increasing the number of CPU cores. Moreover, ParAFEMCap is shown to have the same linear computation complexity as those integral equation methods, which make it very promising for capacitance extraction of large-scale interconnect problems, while ParAFEMThermo also is an effective thermal analysis tool with high computational ability.
Numerical results will demonstrate that ParAFEMCap and ParAFEMThermo have the advantages of high computational efficiency, high accuracy and high parallel scalability.
引文
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