低功耗双界面CPU智能卡芯片的研究与设计
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摘要
目前智能卡根据卡中的集成电路不同可大体分为逻辑加密卡和CPU卡。我国市场上最常见的IC卡是逻辑加密卡,这类IC卡凭借较高的性价比得到了广大用户的青睐,并己被广泛应用于公交、医疗、校园一卡通,门禁等领域。由于逻辑加密卡芯片采用的是流密码技术,密钥长度也不是很长,普遍存在着较大的安全隐患,有被黑客破解的可能。在金融、身份识别、电子护照等对安全要求比较高的领域目前更倾向于使用内嵌微处理器的CPU卡芯片。
CPU卡芯片比逻辑加密卡具有更高的安全性,内部有双重安全机制,第一重是芯片本身集成的加密算法模块；第二重保护则是CPU卡芯片特有的COS(Chip Operating System)系统。除此以外,CPU卡可以实现真正的一卡多用。但是CPU卡芯片比逻辑加密卡芯片设计更复杂,特别是接触式、非接触式双重应用的双界面智能卡芯片设计难度则更大。研制出低功耗高可靠性的双界面CPU卡芯片,已成为国内外智能卡芯片研发机构的工作重点和主攻方向。本论文根据双界面智能卡芯片的应用需求,在低功耗方面开展了针对性的研究。
在双界面智能卡系统架构的基础上,论文针对非接触应用条件下对低功耗要求的特殊性,’采用了低功耗管理、具体电路结构等不同层级总共九种有效低功耗设计方法来降低芯片的峰值功耗,并对功耗仿真结果进行了详细比较。
接着论文首次提出了一种能够根据系统实际运行的负载情况以及能量耦合情况自动调节无源芯片工作频率的方法,即动态频率调整(Dynamic Frequency Scaling)方法。使用该方法后,使得智能卡芯片在非接触应用时,工作距离比不使用该方法(四分频)至少延长了2厘米；在相同耦合距离的条件下,同采用固定频率(八分频)相比,平均交易时间缩短了18%。
论文又详细地介绍了在智能卡芯片设计中,异步电路设计方法相较于同步电路设计方法的巨大优势,并且应用专门描述异步电路的Balsa语言和用于同步电路描述的verilog语言分别实现了DES算法的四相捆绑数据协议的异步电路设计,然后和采用同步电路设计方法的DES算法模块相比较,证明了这两种异步电路设计方法的有效性,以及在低功耗上的优势。
最后论文描述了芯片测试情况,测试了在接触式和非接触式不同应用条件下的交易时间。在两种应用条件下,通过对交易过程中命令的分解,理论推导了交易时间并和仿真结果和芯片的实测结果进行了对比,结果表明芯片的功能和交易速度性能完全符合设计的要求。
Currently smart card can be categorized into two major types:logic encrypt card and CPU card. The most common IC card in civil market is logic encrypt card. The type of IC card is very welcome to the customers due to its high performance price ratio, and it is widely used in public transportation, medicine, one card on campus, entrance guard and so on. But the logic card uses the stream encryption method and its secret key is very short, it can be cracked by hacks easily. The application areas such as finance, identify certified, electronic passport choose the CPU smart cards instead of logic cards.
CPU card chip has dual security mechanisms. One is the chip itself integrates the encryption algorithm module, the other is its specific COS (Chip Operation System). Though the CPU card can indeed realize multi-application, its design is more complex than the normal logic card chip, without saying the dual-interface CPU smart card chip. Many research and development institutions are focusing on exploiting the chip design. The paper makes lots of research to realize the effective low power design for this smart card chip.
Firstly, the paper describes the special low power requirement and challenge by the contactless application and presents nine effecitive low power design methods to lower the average power and peak power for both of contactless and contact applications from architecture level, circuit structure level and software/hardware combination level.
The paper presents a creative method to automatically adjust the working frequency according to smart card real operation load for the first time, we call it as DFS (Dynamic Frequency Scaling) method which is specially used for the passive devices. The test result shows that the longest communication distance is improved from 6cm to 8 cm compared to the same smart card chip using the fixed frequency divided by 4 and the transaction time is saved by 18% in average, compared to the same chip using the fixed frequency divided by 8.
The paper introduces the asynchronous circuits design method in detail. By using balsa language and Verilog languae, we realize the DES asynchrous circuit design based on the four-phase bundled-data protocol. The test results confirm the rightness of the asynchronous design method and its superiority in the low power design for the smart card.
Finally, the paper gives the test result of the real chip and compares the transcation time among calculation, simulation and test results. It shows the chip has good performance for both of the transaction time and the communication distance in contactless application.
CPU卡芯片比逻辑加密卡具有更高的安全性,内部有双重安全机制,第一重是芯片本身集成的加密算法模块；第二重保护则是CPU卡芯片特有的COS(Chip Operating System)系统。除此以外,CPU卡可以实现真正的一卡多用。但是CPU卡芯片比逻辑加密卡芯片设计更复杂,特别是接触式、非接触式双重应用的双界面智能卡芯片设计难度则更大。研制出低功耗高可靠性的双界面CPU卡芯片,已成为国内外智能卡芯片研发机构的工作重点和主攻方向。本论文根据双界面智能卡芯片的应用需求,在低功耗方面开展了针对性的研究。
在双界面智能卡系统架构的基础上,论文针对非接触应用条件下对低功耗要求的特殊性,’采用了低功耗管理、具体电路结构等不同层级总共九种有效低功耗设计方法来降低芯片的峰值功耗,并对功耗仿真结果进行了详细比较。
接着论文首次提出了一种能够根据系统实际运行的负载情况以及能量耦合情况自动调节无源芯片工作频率的方法,即动态频率调整(Dynamic Frequency Scaling)方法。使用该方法后,使得智能卡芯片在非接触应用时,工作距离比不使用该方法(四分频)至少延长了2厘米；在相同耦合距离的条件下,同采用固定频率(八分频)相比,平均交易时间缩短了18%。
论文又详细地介绍了在智能卡芯片设计中,异步电路设计方法相较于同步电路设计方法的巨大优势,并且应用专门描述异步电路的Balsa语言和用于同步电路描述的verilog语言分别实现了DES算法的四相捆绑数据协议的异步电路设计,然后和采用同步电路设计方法的DES算法模块相比较,证明了这两种异步电路设计方法的有效性,以及在低功耗上的优势。
最后论文描述了芯片测试情况,测试了在接触式和非接触式不同应用条件下的交易时间。在两种应用条件下,通过对交易过程中命令的分解,理论推导了交易时间并和仿真结果和芯片的实测结果进行了对比,结果表明芯片的功能和交易速度性能完全符合设计的要求。
Currently smart card can be categorized into two major types:logic encrypt card and CPU card. The most common IC card in civil market is logic encrypt card. The type of IC card is very welcome to the customers due to its high performance price ratio, and it is widely used in public transportation, medicine, one card on campus, entrance guard and so on. But the logic card uses the stream encryption method and its secret key is very short, it can be cracked by hacks easily. The application areas such as finance, identify certified, electronic passport choose the CPU smart cards instead of logic cards.
CPU card chip has dual security mechanisms. One is the chip itself integrates the encryption algorithm module, the other is its specific COS (Chip Operation System). Though the CPU card can indeed realize multi-application, its design is more complex than the normal logic card chip, without saying the dual-interface CPU smart card chip. Many research and development institutions are focusing on exploiting the chip design. The paper makes lots of research to realize the effective low power design for this smart card chip.
Firstly, the paper describes the special low power requirement and challenge by the contactless application and presents nine effecitive low power design methods to lower the average power and peak power for both of contactless and contact applications from architecture level, circuit structure level and software/hardware combination level.
The paper presents a creative method to automatically adjust the working frequency according to smart card real operation load for the first time, we call it as DFS (Dynamic Frequency Scaling) method which is specially used for the passive devices. The test result shows that the longest communication distance is improved from 6cm to 8 cm compared to the same smart card chip using the fixed frequency divided by 4 and the transaction time is saved by 18% in average, compared to the same chip using the fixed frequency divided by 8.
The paper introduces the asynchronous circuits design method in detail. By using balsa language and Verilog languae, we realize the DES asynchrous circuit design based on the four-phase bundled-data protocol. The test results confirm the rightness of the asynchronous design method and its superiority in the low power design for the smart card.
Finally, the paper gives the test result of the real chip and compares the transcation time among calculation, simulation and test results. It shows the chip has good performance for both of the transaction time and the communication distance in contactless application.
引文
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