封装和PCB上电源/地平面的分析和优化
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摘要
因为同步开关噪声产生的噪声电流,电源完整性问题已经成为现今制约整个高速数字系统性能的一个重要问题。作为馈电系统(Power delivery system)不可缺少的一部分,封装和PCB上的电源/地平面为这些噪声电流提供了耦合路径。因此一个设计良好的电源/地平面对于保证整个系统的性能和稳定性都是相当重要的。为了保证设计出一个良好的电源/地平面,对电源/地平面的精确快速分析以及其上噪声的优化都是非常重要的。而在电源/地平面上加入去耦电容是提高电源/地平面性能、保证电源完整性的一个主要的切实可行的方法。
在高性能的高速数字系统的封装和PCB上的电源/地平面上有大量的通孔、去耦电容,并且电源/地平面常常是不规则几何形状的、多层的。电源/地平面结构的复杂性会在对其进行均匀网格划分时制约网格的大小。非常细小的网格将能够保证后续分析的精确性,但这是以CPU时间和内存的损耗为代价的。本文提出了基于非均匀划分的传输矩阵法。这样的方法将更加实用有效,可以用于处理多层的、不规则几何形状的、复杂的电源/地平面模型。本文还将基于非均匀划分的传输矩阵法与模拟退火法结合,开发出电源/地平面上去耦电容自动优化的算法并考虑如何实现应用软件。本文的工作主要有以下几点:
(1)提出非均匀划分思想。
(2)把非均匀划分思想用于传输矩阵法以分析电源/地平面。文章给出了基于非均匀划分的传输矩阵法分析含有大量通孔以及去耦电容的,多层的、不规则几何形状的电源/地平面分析流程。
(3)以此高效的电源/地平面分析方法为基础开发出电源/地平面上去耦电容自动优化的算法,并讨论了如何实现应用程序。为了使基于非均匀划分的传输矩阵法更适合于对去耦电容的优化,文章提出了在去耦电容被插入、删除和更改时加速阻抗矩阵更新的算法。
PI has become a limiting factor for the overall performance of modern chip design due to the current surges caused by SSN. As an indispensable part of the power delivery system, the power/ground (P/G) planes provide coupling paths for the large current flows. And a robust P/G plane design is crucial to meeting performance targets and guaranteeing reliable operations. To ensure the robustness of the design, it is essential to have the exact analysis of the noise on the P/G plane pairs and the optimization of P/G planes to mitigate the noise. Adding in-package decoupling capacitors is one of the most efficient ways to improve the in-package power integrity.
In high performance microprocessors, the package may have many vias, decoupling capacitors, irregular geometries and multiple plane layers. The complex structure and various border effects restrict the size of the segment in regular partitioning when discretizing the P/G planes. A small enough segment would guarantee the accuracy at the cost of memory and CPU time. In this paper, we propose an irregular partitioning strategy in which the P/G planes can be partitioned into different rectangular shapes according to the vias, decoupling capacitors or other details of the structures. Such a strategy is more practical and efficient, because larger segment can be used for non-critical regions and smaller for regions full of vias or decoupling capacitors. We integrate this strategy into TMM to analyze the multiple-layer P/G planes with complex structures. Based on the improved TMM method, we have proposed a methodology for in-package decoupling capacitor optimization on multiple-layer P/G plane. Compared with previous work, our method can gain more accurate results with less CPU runtime. The main contributions of this paper are summarized as follows.
(1)We propose an irregular partitioning strategy to divide the P/G planes. This strategy partitions the planes with different-sized segments depending on the specific structures or requirements.
(2)We apply the irregular partitioning strategy to TMM method. Based on that, we simplify the computation procedure of TMM and give a fast flow for multiple-layer P/G planes analysis.
(3)We use the improved TMM for fast decoupling capacitance allocation. A methodology to guide the decap optimization is also proposed. When decoupling capacitors are added or deleted, we use a matrix refinement technique to speed up the transmission matrix update. Experimental results show that our methodology can optimize the target impedance very efficiently and accurately.
在高性能的高速数字系统的封装和PCB上的电源/地平面上有大量的通孔、去耦电容,并且电源/地平面常常是不规则几何形状的、多层的。电源/地平面结构的复杂性会在对其进行均匀网格划分时制约网格的大小。非常细小的网格将能够保证后续分析的精确性,但这是以CPU时间和内存的损耗为代价的。本文提出了基于非均匀划分的传输矩阵法。这样的方法将更加实用有效,可以用于处理多层的、不规则几何形状的、复杂的电源/地平面模型。本文还将基于非均匀划分的传输矩阵法与模拟退火法结合,开发出电源/地平面上去耦电容自动优化的算法并考虑如何实现应用软件。本文的工作主要有以下几点:
(1)提出非均匀划分思想。
(2)把非均匀划分思想用于传输矩阵法以分析电源/地平面。文章给出了基于非均匀划分的传输矩阵法分析含有大量通孔以及去耦电容的,多层的、不规则几何形状的电源/地平面分析流程。
(3)以此高效的电源/地平面分析方法为基础开发出电源/地平面上去耦电容自动优化的算法,并讨论了如何实现应用程序。为了使基于非均匀划分的传输矩阵法更适合于对去耦电容的优化,文章提出了在去耦电容被插入、删除和更改时加速阻抗矩阵更新的算法。
PI has become a limiting factor for the overall performance of modern chip design due to the current surges caused by SSN. As an indispensable part of the power delivery system, the power/ground (P/G) planes provide coupling paths for the large current flows. And a robust P/G plane design is crucial to meeting performance targets and guaranteeing reliable operations. To ensure the robustness of the design, it is essential to have the exact analysis of the noise on the P/G plane pairs and the optimization of P/G planes to mitigate the noise. Adding in-package decoupling capacitors is one of the most efficient ways to improve the in-package power integrity.
In high performance microprocessors, the package may have many vias, decoupling capacitors, irregular geometries and multiple plane layers. The complex structure and various border effects restrict the size of the segment in regular partitioning when discretizing the P/G planes. A small enough segment would guarantee the accuracy at the cost of memory and CPU time. In this paper, we propose an irregular partitioning strategy in which the P/G planes can be partitioned into different rectangular shapes according to the vias, decoupling capacitors or other details of the structures. Such a strategy is more practical and efficient, because larger segment can be used for non-critical regions and smaller for regions full of vias or decoupling capacitors. We integrate this strategy into TMM to analyze the multiple-layer P/G planes with complex structures. Based on the improved TMM method, we have proposed a methodology for in-package decoupling capacitor optimization on multiple-layer P/G plane. Compared with previous work, our method can gain more accurate results with less CPU runtime. The main contributions of this paper are summarized as follows.
(1)We propose an irregular partitioning strategy to divide the P/G planes. This strategy partitions the planes with different-sized segments depending on the specific structures or requirements.
(2)We apply the irregular partitioning strategy to TMM method. Based on that, we simplify the computation procedure of TMM and give a fast flow for multiple-layer P/G planes analysis.
(3)We use the improved TMM for fast decoupling capacitance allocation. A methodology to guide the decap optimization is also proposed. When decoupling capacitors are added or deleted, we use a matrix refinement technique to speed up the transmission matrix update. Experimental results show that our methodology can optimize the target impedance very efficiently and accurately.
引文
[1]Q.K.Zhu,Power Distribution Network Design for VLSI,John Wiley,2004
[2]The International Technology Roadmap for Semiconductors,http://www.itrs.net,Semiconductor Industry Association,2006
[3]卓成,“超大规模集成电路设计中电源网格的分析及优化”,硕士论文,浙江大学,2007。
[4]E.E.Davidson,"Electrical Design of a High Speed Computer Package," IBM J.RES.DEVELOP,VOL.26,NO.23,MAY 1982,pp.349-361.
[5]Joong-Ho Kim,"Modeling of Package and Board Power Distribution Networks Using Transmission Matrix and Macro-modeling Methods," Ph.D.dissertation,Georgia Institute of Technology,October 2002.
[6]Bradley D.McCredie and Wiren D.Becker,"Modeling,Measurement,and Simulation of Simultaneous Switching Noise," IEEE TRANSACTION ON COMPONENTS,PACKAGING,AND MANUFACTURING TECHNOLOGY-PART.B,VOL.19,NO.3,AUGUST 1996,pp.461-472.
[7]R.R.Tummala,"Microsystems Packaging,New York:McGraw-Hill," 2001
[8]Jiayuan Fang,Dennis Herrell,Jin Zhao,Jingping Zhang and Raymond Chen,"Modeling of the Electrical Performance of the Power and Ground Supply for a PC Microprocessor on a Card,"
[9]Chen,J.,and He,L.,"Efficient In-Package Decoupling Capacitor Optimization for I/O Power Integrity," COMPUTER-AIDED DESIGH OF INTEGRATED CIRCUITS AND SYSTEMS,VOL.26,NO.4,2006,pp.734-738.
[10]I.Novak,"Lossy power distribution network with thin dielectric layers and/or thin conductive layers" IEEE Trans.Com.,Packag.,Manufact.Tchnol.,vol.23,no.3,pp.353-360,Aug.2000
[11]I.Novak,L.D.Smith,and T.Roy,"Low impedance power planes with self damping," in Proc.9~(th)Topical Meeting on Elect.Perform.Electron.Packag.,pp.123-126,Oct.2000
[12]R.Senthinathan,G.Tubbs,and M.Schuelein,"Negative feedback influence on simultaneous switching CMOS outputs," in Proc.IEEE Custom Integrated Circuits Conf.,pp.5.4.1-5.4.5,1988
[13]A.Vaidyanath,B.Thorodsdsen,and J.Prince,"Modeling of simultaneous switching noise for CMOS output drivers",TECHCON Extended Abstracts,pp.311-313,1993
[14]Fang,J.,Liu,Y.,Chen,Y.,Wu,Z.,Agrawal,A.,1993.Modeling of power/ground plane noise in high speed digital electronics packaging,Electrical Performance of Electronic Packaging,p.206-208.[doi:10.1109/EPEP.1993.394553]
[15]Wang,H.G.,Chan,C.H.,Tsang,L.,2004.A new multilevel Green's function interpolation method for large scale EM simulations in RF Ics,IEEE Antennas and Propagation Society International Symposium,p.1182-1186.
[16]Phillips,J.R.,White,J.K.,1997.A precorrected-FFT method for electrostatic analysis of complicated 3-D structures,IEEE Trans.Computer-Aided Design of Integrated Circuits andsysfems,16(10):1059-1072.
[17]Li,S.Q.,Yu,Y.X.,Chan,C,F.,Chan,K.F.,Tsang,L.,2001.A sparse-matrix/canonical grid method for analyzing densely packed interconnects,IEEE Trans.Microwave Theory Tech.,49(7):1221-1228.[doi:10.1109/22.932239]
[18]Nanju Na,Jinseong Choi,Sungjun Chun,Madhavan Swaminathan,and Jegannathan Srinivasan,"Modeling and Transient Simulation of Planes in Electronic Packages," IEEE TRANSACTIONS ON ADVANCED PACKAGING,VOL.23,NO.23,AUGUST 2000,pp.340-352.
[19]Ken Lee and Alan Barber,"Modeling and Analysis of Multichip Module Power Supply Planes," IEEE Trans.Compon.,Packag.,Manuf.B,vol 18,no 4,pp.628-639,Nov.1995
[20]Wang,C.,Mao,J.K.,Selli,C.,Luan,S.F.,Zhang,L.,Fan,J.,Pommerenke,D.J.,DuBroff,R.E.,and Drewniak,J.L.,"An Efficient Approach for Power Delivery Network Design with Closed-form Expressions for Parasitic Interconnect Inductances," IEEE TRANSACTION ON ADVANCED PACKAGE,VOL.29,NO.2,2006,pp.320-334.
[21]Kim,J.H.,Swaminathan,M.,2001.Modeling of Irregular Shaped Power Distribution Planes Using Transmission Matrix Method,IEEE Trans.Advanced Packaging,24(3):334-336.
[22]Kim,J.H.,Swaminathan,M.,2002.Modeling of Multilayered Power Distribution Planes Using Transmission Matrix Method, IEEE Trans. Advanced Packaging, 25(2): 189-199.
[23] I. Hattori, A. Kamo, T. Watanabe, and H. Asai, "A searching method for optimal locations of decoupling capacitors based on electromagnetic field analysis by FDTD method, "in IEEE Topical Meeting on Electrical Performance of Electronic Packaging, 2002.
[24]H. Zheng, B. Krauter, and L. Pileggi, "On-package decoupling optimization with package macromodels," in Custom Integrated Circuits Conference, 2003
[25] Zheng, H, Krauter, B., and Pileggi, L.T., "On-Package Decoupling Optimization with Package Macromodels," Proceedings of IEEE 2003. CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2003, pp. 723-726.
[26] D.A. Al-Mukhtar and J.E. Sitch, "Transmission-line matrix method with irregularly graded space," Proc. Inst. Elect. Eng. H, vol. 128, pp. 299-305, Dec, 1981.
[27] I. Novak, "Reducing simultaneous switching noise and EMI on ground/power planes by dissipative edge termination," in Proc. 7th Topical meeting on Elect. Perform. Electron. Packag., pp. 181-184, Oct. 1998
[29] Henry Hungjen Wu, Jeffrey W. Meyer, Keunmyung Lee, and Alan Barber, "Accurate Power Supply and Ground Plane Pair Model," IEEE TRANSACTION ON ADVANCED PACKAGING, VOL. 22, NO. 3, AUGUST 1999, pp. 259-266.
[28] Istvan Novak, Jason R. Miller, and Eric Blomberg, "Simulating Complex Power-Ground Plane Shapes with Variable-Size Cell SPICE Grids,"
[30] Chen, K.S., 2001. Applied Electromagnetism, Zhejiang University Press, Hangzhou, p.76-109 (in Chinese)
[31] www.sfcode.cn
[32] Lee, J., Dragos, M.H., Iyer, M.K., Kim H., Kim, J., 2005. Analysis and suppression of SSN noise coupling between power/ground plane cavities through cutouts in multilayer packages and PCBs, ADVANCED PACKAGING, 28(2): 298-309. [doi: 10.1109/TADVP.2005.846932]
[2]The International Technology Roadmap for Semiconductors,http://www.itrs.net,Semiconductor Industry Association,2006
[3]卓成,“超大规模集成电路设计中电源网格的分析及优化”,硕士论文,浙江大学,2007。
[4]E.E.Davidson,"Electrical Design of a High Speed Computer Package," IBM J.RES.DEVELOP,VOL.26,NO.23,MAY 1982,pp.349-361.
[5]Joong-Ho Kim,"Modeling of Package and Board Power Distribution Networks Using Transmission Matrix and Macro-modeling Methods," Ph.D.dissertation,Georgia Institute of Technology,October 2002.
[6]Bradley D.McCredie and Wiren D.Becker,"Modeling,Measurement,and Simulation of Simultaneous Switching Noise," IEEE TRANSACTION ON COMPONENTS,PACKAGING,AND MANUFACTURING TECHNOLOGY-PART.B,VOL.19,NO.3,AUGUST 1996,pp.461-472.
[7]R.R.Tummala,"Microsystems Packaging,New York:McGraw-Hill," 2001
[8]Jiayuan Fang,Dennis Herrell,Jin Zhao,Jingping Zhang and Raymond Chen,"Modeling of the Electrical Performance of the Power and Ground Supply for a PC Microprocessor on a Card,"
[9]Chen,J.,and He,L.,"Efficient In-Package Decoupling Capacitor Optimization for I/O Power Integrity," COMPUTER-AIDED DESIGH OF INTEGRATED CIRCUITS AND SYSTEMS,VOL.26,NO.4,2006,pp.734-738.
[10]I.Novak,"Lossy power distribution network with thin dielectric layers and/or thin conductive layers" IEEE Trans.Com.,Packag.,Manufact.Tchnol.,vol.23,no.3,pp.353-360,Aug.2000
[11]I.Novak,L.D.Smith,and T.Roy,"Low impedance power planes with self damping," in Proc.9~(th)Topical Meeting on Elect.Perform.Electron.Packag.,pp.123-126,Oct.2000
[12]R.Senthinathan,G.Tubbs,and M.Schuelein,"Negative feedback influence on simultaneous switching CMOS outputs," in Proc.IEEE Custom Integrated Circuits Conf.,pp.5.4.1-5.4.5,1988
[13]A.Vaidyanath,B.Thorodsdsen,and J.Prince,"Modeling of simultaneous switching noise for CMOS output drivers",TECHCON Extended Abstracts,pp.311-313,1993
[14]Fang,J.,Liu,Y.,Chen,Y.,Wu,Z.,Agrawal,A.,1993.Modeling of power/ground plane noise in high speed digital electronics packaging,Electrical Performance of Electronic Packaging,p.206-208.[doi:10.1109/EPEP.1993.394553]
[15]Wang,H.G.,Chan,C.H.,Tsang,L.,2004.A new multilevel Green's function interpolation method for large scale EM simulations in RF Ics,IEEE Antennas and Propagation Society International Symposium,p.1182-1186.
[16]Phillips,J.R.,White,J.K.,1997.A precorrected-FFT method for electrostatic analysis of complicated 3-D structures,IEEE Trans.Computer-Aided Design of Integrated Circuits andsysfems,16(10):1059-1072.
[17]Li,S.Q.,Yu,Y.X.,Chan,C,F.,Chan,K.F.,Tsang,L.,2001.A sparse-matrix/canonical grid method for analyzing densely packed interconnects,IEEE Trans.Microwave Theory Tech.,49(7):1221-1228.[doi:10.1109/22.932239]
[18]Nanju Na,Jinseong Choi,Sungjun Chun,Madhavan Swaminathan,and Jegannathan Srinivasan,"Modeling and Transient Simulation of Planes in Electronic Packages," IEEE TRANSACTIONS ON ADVANCED PACKAGING,VOL.23,NO.23,AUGUST 2000,pp.340-352.
[19]Ken Lee and Alan Barber,"Modeling and Analysis of Multichip Module Power Supply Planes," IEEE Trans.Compon.,Packag.,Manuf.B,vol 18,no 4,pp.628-639,Nov.1995
[20]Wang,C.,Mao,J.K.,Selli,C.,Luan,S.F.,Zhang,L.,Fan,J.,Pommerenke,D.J.,DuBroff,R.E.,and Drewniak,J.L.,"An Efficient Approach for Power Delivery Network Design with Closed-form Expressions for Parasitic Interconnect Inductances," IEEE TRANSACTION ON ADVANCED PACKAGE,VOL.29,NO.2,2006,pp.320-334.
[21]Kim,J.H.,Swaminathan,M.,2001.Modeling of Irregular Shaped Power Distribution Planes Using Transmission Matrix Method,IEEE Trans.Advanced Packaging,24(3):334-336.
[22]Kim,J.H.,Swaminathan,M.,2002.Modeling of Multilayered Power Distribution Planes Using Transmission Matrix Method, IEEE Trans. Advanced Packaging, 25(2): 189-199.
[23] I. Hattori, A. Kamo, T. Watanabe, and H. Asai, "A searching method for optimal locations of decoupling capacitors based on electromagnetic field analysis by FDTD method, "in IEEE Topical Meeting on Electrical Performance of Electronic Packaging, 2002.
[24]H. Zheng, B. Krauter, and L. Pileggi, "On-package decoupling optimization with package macromodels," in Custom Integrated Circuits Conference, 2003
[25] Zheng, H, Krauter, B., and Pileggi, L.T., "On-Package Decoupling Optimization with Package Macromodels," Proceedings of IEEE 2003. CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2003, pp. 723-726.
[26] D.A. Al-Mukhtar and J.E. Sitch, "Transmission-line matrix method with irregularly graded space," Proc. Inst. Elect. Eng. H, vol. 128, pp. 299-305, Dec, 1981.
[27] I. Novak, "Reducing simultaneous switching noise and EMI on ground/power planes by dissipative edge termination," in Proc. 7th Topical meeting on Elect. Perform. Electron. Packag., pp. 181-184, Oct. 1998
[29] Henry Hungjen Wu, Jeffrey W. Meyer, Keunmyung Lee, and Alan Barber, "Accurate Power Supply and Ground Plane Pair Model," IEEE TRANSACTION ON ADVANCED PACKAGING, VOL. 22, NO. 3, AUGUST 1999, pp. 259-266.
[28] Istvan Novak, Jason R. Miller, and Eric Blomberg, "Simulating Complex Power-Ground Plane Shapes with Variable-Size Cell SPICE Grids,"
[30] Chen, K.S., 2001. Applied Electromagnetism, Zhejiang University Press, Hangzhou, p.76-109 (in Chinese)
[31] www.sfcode.cn
[32] Lee, J., Dragos, M.H., Iyer, M.K., Kim H., Kim, J., 2005. Analysis and suppression of SSN noise coupling between power/ground plane cavities through cutouts in multilayer packages and PCBs, ADVANCED PACKAGING, 28(2): 298-309. [doi: 10.1109/TADVP.2005.846932]