用于信号完整性的IBIS建模与仿真方法研究
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摘要
深亚微米设计带来了大量的挑战,当涉及到信号完整性时,高速的数字信号不能简单的用逻辑的0和1来表征,需要使用模拟量来描述,而晶体管级模型的仿真速度是进行系统级高速仿真的瓶颈。
本文描述了一种对数字电路输入输出端口电路进行建模的标准,IBIS。它可以替代晶体管级的模型进行电路仿真和信号完整性分析。文章首先对工作频率在1GB的DDR-SDRAM的数据输出端口建立IBIS模型,并通过特征点比较,差值比较的方法,对模型进行了验证。在此基础上,对输出缓冲器模型仿真方法进行研究,提出一种新的仿真方法,能够消除输出缓冲器IBIS模型的瞬态仿真中对伴随电容的重复计算误差。考虑到,经过传输线的信号将带有斜率和延迟,本文对非理想输入给IBIS仿真带来的影响做出分析,并且采用一种新的仿真方法,使得IBIS模型能够准确的响应非理想信号激励。
Deep submicron circuit design brings lots of challenges. When come to signal integrity, digital signal can not be simply treated as logic“1”or“0”. It is useful to describe them as analog signal. But simulation on transistor level is time-consuming which can not be used on system level.
Some basic concepts in IBIS are reviewed in this paper. The process to generate and verify an IBIS output model for a DDR-SDRAM which works on 1 GHz is described. A simulation method is proposed to eliminate the double count of company capacitance in transient simulation. Transition time should be considered when the signal transfer through transmission line, it brings slope to input signals. In this paper, a novel circuit structure is introduced which can improve the accuracy of the non ideal input IBIS simulation.
本文描述了一种对数字电路输入输出端口电路进行建模的标准,IBIS。它可以替代晶体管级的模型进行电路仿真和信号完整性分析。文章首先对工作频率在1GB的DDR-SDRAM的数据输出端口建立IBIS模型,并通过特征点比较,差值比较的方法,对模型进行了验证。在此基础上,对输出缓冲器模型仿真方法进行研究,提出一种新的仿真方法,能够消除输出缓冲器IBIS模型的瞬态仿真中对伴随电容的重复计算误差。考虑到,经过传输线的信号将带有斜率和延迟,本文对非理想输入给IBIS仿真带来的影响做出分析,并且采用一种新的仿真方法,使得IBIS模型能够准确的响应非理想信号激励。
Deep submicron circuit design brings lots of challenges. When come to signal integrity, digital signal can not be simply treated as logic“1”or“0”. It is useful to describe them as analog signal. But simulation on transistor level is time-consuming which can not be used on system level.
Some basic concepts in IBIS are reviewed in this paper. The process to generate and verify an IBIS output model for a DDR-SDRAM which works on 1 GHz is described. A simulation method is proposed to eliminate the double count of company capacitance in transient simulation. Transition time should be considered when the signal transfer through transmission line, it brings slope to input signals. In this paper, a novel circuit structure is introduced which can improve the accuracy of the non ideal input IBIS simulation.
引文
[1] Peivand F. Tehrani, Yuzhe Chen, Jiayuan Fang,Department of Electrical Engineering, State University of New York at Binghamton, “Extraction of Transient Behavioral Model of Digital I/O Buffers from IBIS”, 1996 Electronic Components and Technology Conference, PP:1009-1015,
[2] Ying Wang, Han Ngee Tan, School of EEE, Nanyang Technological University, Singapore “The Development of Analog SPICE Behavioral Model Based on IBIS Model”, 4-6 March 1999 , VLSI, 1999. Proceedings. PP:101 - 104
[3] Bob Ross, Syed Huq, Jon Powell, EIA IBIS Open Forum Committee “IBIS Models for Signal Integrity Applications” , EE Times, 1996, 18(9).38～43
[4] A.Varma, M.Steer, P.Franzor “Developing Improved 10 Buffer Behavioral Modeling Methodology Based on IBIS” 2006 IEEE Electrical Performance of Electronic Packaging P 69-72
[5] Arpad Muranyi, Signal Integrity Engineering, Intel Corporation, “Introduction to IBIS models and IBIS model making”, Intel Corporation Folsom, CA November 3-4, 2003
[6] Arpad Muranyi, Signal Integrity Engineering, Intel Corporation, “I-V curve linearity and buffer impedance”, IBIS Summit at DAC 2004 Manchester Grand Hyatt Hotel, Santa Diego, CA June 8, 2004
[7] Bob Ross, Interconnectix Business Unit, Mentor Graphics Corporation, “Introduction & Model Processing Algorithms”, IBIS Summit Meeting, Boxboro, MA October 15, 1998
[8] Jinhua Chen, North East Systems Associates, Inc. “Comparison between SPICE and IBIS I/O Device Simulations” IBIS Summit at DAC 2004 Manchester Grand Hyatt Hotel, Santa Diego, CA June 8, 2004
[9] Bob Ross, Interconnectix Business Unit, “IBIS Die V-T Tables from Part or Board Measurements” DesignConIBIS Summit Meeting Santa Clara, California February 2, 2004
[10] Ambrish Varma, Michael Steer, Paul Franzon, “A New Method to Achieve Improved Accuracy with IBIS Models” IBIS Summit at DAC 2004 Manchester Grand Hyatt Hotel, Santa Diego, CA June 8, 2004
[11] Roland H.G.Cuny, Development Support, Siemens Nixdorf Informationsystems AG, Paderbom, Germany, “SPICE and IBIS Modeling Kits the Basis for Signal Integrity Analyses” Electromagnetic Compatibility 19-23 Aug. 1996 PP:204 - 208
[12] Jerry D Hayes and Larry Wissel, IBM Microelectronics Division, “Behavioral Modeling for Timing, Noise, and Signal Integrity Analysis”
[13] “IBIS (I/O Buffer Information Specification)”, The IBIS Open Forum, Version 3.2, August 1999.
[14] Peters S., “IBIS Forum I/O Buffer Modeling Cookbook”, the IBIS Open Forum, Revision 2.0X
[15] Lance Wang, ZhangMinZhong Cadence Design Systems, Inc. “Using IBIS for SI Analysis” Asian IBIS Summit, ShenZhen, P.R. ChinaDecember 6, 2005
[16] Technology and Research Labs “Code (Equation) Based Models, an accurate way to represent, and transfer simulation models”
[17] Bob Ross, Interconnectix Business Unit, “I-T Tables and BIRD42.3 Revisited” IBIS Summit Meeting Design Automation Conference 2004 San Diego, California June 8, 2004
[18] P. Forstner, "Input and Output Characteristics of Digital Integrated Circuits", Application Report, Texas Instruments, August 1994.
[19] Arpad Muranyi,Signal Integrity Engineering,Intel Corporation “An algorithm to model overclocking more accurately” IBIS Summit at DesignConEast 2003 Royal Plaza Hotel, Marlborough, MA June 23, 2003
[20] Bob Ross, “Buffers for Advanced SPICE to IBIS Testing” IBIS Summit Meeting Design Automation Conference 2006 San Francisco, California July 25, 2006
[21] F. G. Canavero, I. A. Maio, I. S. Stievano, “Identification of Models for Digital Integrated Circuit Ports from Measured Transient Waveforms” IEEE Instrumentation and Measurement Technology Conference Budapest, Hungary, May 21-23, 2001
[22] F. G. Canavero, I. A. Maio, I. S. Stievano, “Black-Box Models of Digital IC ports for EMC simulations,” in IEEE International Zurich Symposium on Electromagnetic Compatibility, Zurich, CH, February 20-22, 2001.
[23] Stephen, Garrett, James, “High-Speed Digital System Design : A Handbook of Interconnect Theory and Design Practices” H.Hall, W.Hall, A.McCall
[24] Brian Young “Digital Signal Integrity-Modeling and Simulation withInterconnects and Package” Prentice-Hall PTR
[25] Eric Bogatin “Signal Integrity: Simplified” Pearson Education Prentice Hall
[26] “HSPICE? Simulation and Analysis User Guide”, SYNOPSYS
[27] “HSPICE? Signal Integrity User Guide”, SYNOPSYS
[28] MT74Hx DDR-SDRAM Data Sheet, Micron, http://download.micron.com/pdf/datasheets/dram/ddr2/1GbDDR2.pdf
[29] 蔡兴建,毛军发,陈建华,李征帆 高速数字 IO 缓冲器瞬态行为建模及其在同步开关噪声分析中的应用 电子学报 2000 年第 11 期 PP.36-38,42
[30] 陈建华,毛军发,蔡兴建 王德东 基于 IBIS 模型的 CMOS 电路同步开关噪声的计算和优化 上海交通大学学报 2001 年 35 卷第六期 PP:848-851
[31] 方国华,刘光斌,余志勇 基于 IBIS 模型的信号完整性仿真分析 计算机科学与技术 2004 年 12 月第六期 PP:68-71
[32] 石章如,IBIS 模型的仿真研究与应用分析 武汉理工大学学报 2005 年第 5期 PP 9-12
[33] 童智勇,韩月秋 基于 IBIS 模型的仿真分析在高速 DSP 系统设计中的应用 电子技术应用 2000 年第 12 期 PP:13-15
[2] Ying Wang, Han Ngee Tan, School of EEE, Nanyang Technological University, Singapore “The Development of Analog SPICE Behavioral Model Based on IBIS Model”, 4-6 March 1999 , VLSI, 1999. Proceedings. PP:101 - 104
[3] Bob Ross, Syed Huq, Jon Powell, EIA IBIS Open Forum Committee “IBIS Models for Signal Integrity Applications” , EE Times, 1996, 18(9).38～43
[4] A.Varma, M.Steer, P.Franzor “Developing Improved 10 Buffer Behavioral Modeling Methodology Based on IBIS” 2006 IEEE Electrical Performance of Electronic Packaging P 69-72
[5] Arpad Muranyi, Signal Integrity Engineering, Intel Corporation, “Introduction to IBIS models and IBIS model making”, Intel Corporation Folsom, CA November 3-4, 2003
[6] Arpad Muranyi, Signal Integrity Engineering, Intel Corporation, “I-V curve linearity and buffer impedance”, IBIS Summit at DAC 2004 Manchester Grand Hyatt Hotel, Santa Diego, CA June 8, 2004
[7] Bob Ross, Interconnectix Business Unit, Mentor Graphics Corporation, “Introduction & Model Processing Algorithms”, IBIS Summit Meeting, Boxboro, MA October 15, 1998
[8] Jinhua Chen, North East Systems Associates, Inc. “Comparison between SPICE and IBIS I/O Device Simulations” IBIS Summit at DAC 2004 Manchester Grand Hyatt Hotel, Santa Diego, CA June 8, 2004
[9] Bob Ross, Interconnectix Business Unit, “IBIS Die V-T Tables from Part or Board Measurements” DesignConIBIS Summit Meeting Santa Clara, California February 2, 2004
[10] Ambrish Varma, Michael Steer, Paul Franzon, “A New Method to Achieve Improved Accuracy with IBIS Models” IBIS Summit at DAC 2004 Manchester Grand Hyatt Hotel, Santa Diego, CA June 8, 2004
[11] Roland H.G.Cuny, Development Support, Siemens Nixdorf Informationsystems AG, Paderbom, Germany, “SPICE and IBIS Modeling Kits the Basis for Signal Integrity Analyses” Electromagnetic Compatibility 19-23 Aug. 1996 PP:204 - 208
[12] Jerry D Hayes and Larry Wissel, IBM Microelectronics Division, “Behavioral Modeling for Timing, Noise, and Signal Integrity Analysis”
[13] “IBIS (I/O Buffer Information Specification)”, The IBIS Open Forum, Version 3.2, August 1999.
[14] Peters S., “IBIS Forum I/O Buffer Modeling Cookbook”, the IBIS Open Forum, Revision 2.0X
[15] Lance Wang, ZhangMinZhong Cadence Design Systems, Inc. “Using IBIS for SI Analysis” Asian IBIS Summit, ShenZhen, P.R. ChinaDecember 6, 2005
[16] Technology and Research Labs “Code (Equation) Based Models, an accurate way to represent, and transfer simulation models”
[17] Bob Ross, Interconnectix Business Unit, “I-T Tables and BIRD42.3 Revisited” IBIS Summit Meeting Design Automation Conference 2004 San Diego, California June 8, 2004
[18] P. Forstner, "Input and Output Characteristics of Digital Integrated Circuits", Application Report, Texas Instruments, August 1994.
[19] Arpad Muranyi,Signal Integrity Engineering,Intel Corporation “An algorithm to model overclocking more accurately” IBIS Summit at DesignConEast 2003 Royal Plaza Hotel, Marlborough, MA June 23, 2003
[20] Bob Ross, “Buffers for Advanced SPICE to IBIS Testing” IBIS Summit Meeting Design Automation Conference 2006 San Francisco, California July 25, 2006
[21] F. G. Canavero, I. A. Maio, I. S. Stievano, “Identification of Models for Digital Integrated Circuit Ports from Measured Transient Waveforms” IEEE Instrumentation and Measurement Technology Conference Budapest, Hungary, May 21-23, 2001
[22] F. G. Canavero, I. A. Maio, I. S. Stievano, “Black-Box Models of Digital IC ports for EMC simulations,” in IEEE International Zurich Symposium on Electromagnetic Compatibility, Zurich, CH, February 20-22, 2001.
[23] Stephen, Garrett, James, “High-Speed Digital System Design : A Handbook of Interconnect Theory and Design Practices” H.Hall, W.Hall, A.McCall
[24] Brian Young “Digital Signal Integrity-Modeling and Simulation withInterconnects and Package” Prentice-Hall PTR
[25] Eric Bogatin “Signal Integrity: Simplified” Pearson Education Prentice Hall
[26] “HSPICE? Simulation and Analysis User Guide”, SYNOPSYS
[27] “HSPICE? Signal Integrity User Guide”, SYNOPSYS
[28] MT74Hx DDR-SDRAM Data Sheet, Micron, http://download.micron.com/pdf/datasheets/dram/ddr2/1GbDDR2.pdf
[29] 蔡兴建,毛军发,陈建华,李征帆 高速数字 IO 缓冲器瞬态行为建模及其在同步开关噪声分析中的应用 电子学报 2000 年第 11 期 PP.36-38,42
[30] 陈建华,毛军发,蔡兴建 王德东 基于 IBIS 模型的 CMOS 电路同步开关噪声的计算和优化 上海交通大学学报 2001 年 35 卷第六期 PP:848-851
[31] 方国华,刘光斌,余志勇 基于 IBIS 模型的信号完整性仿真分析 计算机科学与技术 2004 年 12 月第六期 PP:68-71
[32] 石章如,IBIS 模型的仿真研究与应用分析 武汉理工大学学报 2005 年第 5期 PP 9-12
[33] 童智勇,韩月秋 基于 IBIS 模型的仿真分析在高速 DSP 系统设计中的应用 电子技术应用 2000 年第 12 期 PP:13-15