甚短距离光互联系统高速并行帧同步电路设计
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摘要
随着Internet网络和电信网络的快速发展,各种视频音频多媒体通信的广泛应用,对网络的带宽要求越来越大,光纤通信已经成为信息高速公路的基石。
目前,大量的光网络设备被放置于电信服务提供商的同一机房里。为了降低不同设备间采用高速光互联的成本,光互连论坛(Optical Internetworking Forum,OIF)制订了一系列应用于甚短距离(very short reach,VSR)光互联的协议,也即是VSR接口协议,其核心是采用低速并行光链路代替高速串行的光链路,以降低成本。目前OIF制订的VSR接口有10Gbit/s VSR4接口规范和40Gbit/s VSR5接口规范。本文中所研究的VSR4-1为10Gbit/s STM-64/OC-192 SDH/SONET VSR4接口规范中的一个应用协议,它将STM-64/OC-192帧格式数据匹配到十二路并行低速光纤通道上传输。
帧同步电路是数字传输系统中的重要组成部分。VSR帧同步系统是VSR转换集成电路的重要组成部分,STM-64/OC-192的数据经过分割排列、编码、插入校验码、帧定界符插入等处理匹配到十二路1.25Gbit/s通道上,形成具有新的帧结构的数据流,在接收端VSR帧同步系统通过搜捕帧同步码组将接收到的数据重新按照帧结构排列,与发送端保持帧同步,即是将十二路未同步数据转换成十二路同步数据。帧同步的实现方法有逐位调整法和置位调整法,经比较分析,采用置位调整法。结合VSR十二路通道并行传输STM-64/OC-192帧数据的特点,分析了帧同步系统主要性能参数,参考ITU-T的G.783建议中对SDH帧同步性能要求的建议,选取了符合VSR并行传输结构和满足SDH性能要求的参数。为了提高系统的稳定性,在电路上采用并行帧同步电路结构,并采用搜捕校验、同步保护增加系统抗干扰性能。采用自顶向下的设计方法,用Verilog HDL硬件描述语言对VSR十二路帧同步系统进行描述,论文中给出了各个电路的结构和仿真结果。同时设计了基于m序列的高速误码检测系统辅助该帧同步系统和VSR系统的测试。
采用现场可编程门阵列实现了该帧同步系统,作为VSR实验系统的关键模块之一的VSR帧同步电路最后在实际系统上测试通过,通过测试结果表明该帧同步系统能够实际应用,达到了设计目标,在VSR实验系统中工作稳定。
With the fast development of Internet and telecommunications, the extensive application of multimedia communication of audio and video , the bandwidth of networks was required bigger and bigger, the optic communication has already become the foundation of the information superhighway, synchronous digital hierarchy (SDH) already became the world’s high speed communication standard.
At present, a large amount of optic network equipment is put in the same room of the service provider of the telecommunications. In order to reduce the cost of interconnecting between high speed optical equipments, optical internetworking forum (OIF) had made a serial of implementation agreements of optic interlink within very short distance, namely VSR interface agreements. Its key intention is to replace high speed serial parallel optic link with low-speed parallel optic link for lower costs. VSR is a kind of physics layers transmitting technology. At present, OIF had put forward VSR interface implementation agreements of 10Gbit/s and 40Gbit/s.VSR4-1 interface, which are studied in this article, is one of the 10Gbit/s STM-64/OC-192 VSR4 interface agreements. STM-64/OC-192 (10Gbit/s) frames are matched into parallel low-speed fibers, with 12 pairs of 850 nm multimode fibers of 1.25Gbit/s to complete full-duplex transmission. Converter integrated circuit of VSR4-1 maps STM-64/OC-192 frame into parallel optical interfaces, adding corresponding checking and correcting process.
The frame synchronism circuit is the most important part of the digital transmission system.The VSR frame synchronism circuit is the most important part of the VSR system. The data of STM-64/OC-192 are striped and allied, coded, inserted the error correcting code and the frame delimiter, then transmitted through the 12 fibers, forming data stream of a new frame structure. At the receive direction, the VSR frame synchronism circuit re-allied the frame structure and make sure that the data of receive direction are synchronized with the transmit direction.
Frame can be synchronized by two methods. Adopt the set adjusting method after the comparing and analyzing. On the base of the characters of STM-64/OC-192 data through the 12 VSR data channels, refer to the SDH frame synchronizing performance requirement of G.783 recommendation, choose the corresponding transmit structure and parameters to meet the SDH performance requirements.
In order to raise the stability of the system, the parallel frame synchronism circuit is choosed. Following the up-down design technique, we implement the 12 channels frame synchronism circuit with Verilog HDL. The structures and simulate results of the circuits are presented in this paper. Along with the frame synchronism circuit, the bit error test system is designed in this paper.
Adopting the field programmable gate array (FPGA) to implement the frame synchronism system, the VSR frame synchronism circuit is tested in the actual system as the most important module of the VSR system. It is proved that the frame synchronism system is practical and stable. The test results are presented in the paper.
目前,大量的光网络设备被放置于电信服务提供商的同一机房里。为了降低不同设备间采用高速光互联的成本,光互连论坛(Optical Internetworking Forum,OIF)制订了一系列应用于甚短距离(very short reach,VSR)光互联的协议,也即是VSR接口协议,其核心是采用低速并行光链路代替高速串行的光链路,以降低成本。目前OIF制订的VSR接口有10Gbit/s VSR4接口规范和40Gbit/s VSR5接口规范。本文中所研究的VSR4-1为10Gbit/s STM-64/OC-192 SDH/SONET VSR4接口规范中的一个应用协议,它将STM-64/OC-192帧格式数据匹配到十二路并行低速光纤通道上传输。
帧同步电路是数字传输系统中的重要组成部分。VSR帧同步系统是VSR转换集成电路的重要组成部分,STM-64/OC-192的数据经过分割排列、编码、插入校验码、帧定界符插入等处理匹配到十二路1.25Gbit/s通道上,形成具有新的帧结构的数据流,在接收端VSR帧同步系统通过搜捕帧同步码组将接收到的数据重新按照帧结构排列,与发送端保持帧同步,即是将十二路未同步数据转换成十二路同步数据。帧同步的实现方法有逐位调整法和置位调整法,经比较分析,采用置位调整法。结合VSR十二路通道并行传输STM-64/OC-192帧数据的特点,分析了帧同步系统主要性能参数,参考ITU-T的G.783建议中对SDH帧同步性能要求的建议,选取了符合VSR并行传输结构和满足SDH性能要求的参数。为了提高系统的稳定性,在电路上采用并行帧同步电路结构,并采用搜捕校验、同步保护增加系统抗干扰性能。采用自顶向下的设计方法,用Verilog HDL硬件描述语言对VSR十二路帧同步系统进行描述,论文中给出了各个电路的结构和仿真结果。同时设计了基于m序列的高速误码检测系统辅助该帧同步系统和VSR系统的测试。
采用现场可编程门阵列实现了该帧同步系统,作为VSR实验系统的关键模块之一的VSR帧同步电路最后在实际系统上测试通过,通过测试结果表明该帧同步系统能够实际应用,达到了设计目标,在VSR实验系统中工作稳定。
With the fast development of Internet and telecommunications, the extensive application of multimedia communication of audio and video , the bandwidth of networks was required bigger and bigger, the optic communication has already become the foundation of the information superhighway, synchronous digital hierarchy (SDH) already became the world’s high speed communication standard.
At present, a large amount of optic network equipment is put in the same room of the service provider of the telecommunications. In order to reduce the cost of interconnecting between high speed optical equipments, optical internetworking forum (OIF) had made a serial of implementation agreements of optic interlink within very short distance, namely VSR interface agreements. Its key intention is to replace high speed serial parallel optic link with low-speed parallel optic link for lower costs. VSR is a kind of physics layers transmitting technology. At present, OIF had put forward VSR interface implementation agreements of 10Gbit/s and 40Gbit/s.VSR4-1 interface, which are studied in this article, is one of the 10Gbit/s STM-64/OC-192 VSR4 interface agreements. STM-64/OC-192 (10Gbit/s) frames are matched into parallel low-speed fibers, with 12 pairs of 850 nm multimode fibers of 1.25Gbit/s to complete full-duplex transmission. Converter integrated circuit of VSR4-1 maps STM-64/OC-192 frame into parallel optical interfaces, adding corresponding checking and correcting process.
The frame synchronism circuit is the most important part of the digital transmission system.The VSR frame synchronism circuit is the most important part of the VSR system. The data of STM-64/OC-192 are striped and allied, coded, inserted the error correcting code and the frame delimiter, then transmitted through the 12 fibers, forming data stream of a new frame structure. At the receive direction, the VSR frame synchronism circuit re-allied the frame structure and make sure that the data of receive direction are synchronized with the transmit direction.
Frame can be synchronized by two methods. Adopt the set adjusting method after the comparing and analyzing. On the base of the characters of STM-64/OC-192 data through the 12 VSR data channels, refer to the SDH frame synchronizing performance requirement of G.783 recommendation, choose the corresponding transmit structure and parameters to meet the SDH performance requirements.
In order to raise the stability of the system, the parallel frame synchronism circuit is choosed. Following the up-down design technique, we implement the 12 channels frame synchronism circuit with Verilog HDL. The structures and simulate results of the circuits are presented in this paper. Along with the frame synchronism circuit, the bit error test system is designed in this paper.
Adopting the field programmable gate array (FPGA) to implement the frame synchronism system, the VSR frame synchronism circuit is tested in the actual system as the most important module of the VSR system. It is proved that the frame synchronism system is practical and stable. The test results are presented in the paper.
引文
[1] Optical Internetworking Forum.Very Short Reach (VSR) OC-192/STM-64 Interface Based on Parallel Optics.2000,12
[2] ITU-T Recommendation G.783.Characteristics of synchronous digital hierarchy (SDH) equipment functional blocks.1997
[3] M.S.Obaidat,J.Teng.A methodology to analyze the performance of a parallel frame synchronization scheme in SDH high speed networks.Computer Communications 22.1999
[4] Jun Teng,Lei-min Li,M.S.Obaidat.155.52 Mbit/s parallel frame synchronous scheme for SDH networks.Computers and Communications,Conference Proceedings of the 1996 IEEE Fifteenth Annual International Phoenix Conference.1996,3
[5] D.Bajic,J.Stojanovic.Frame-Alignment Monitoring For STM-1 Frame.Communications,IEEE.2001,6
[6] Sha Yanping,Wang Hansheng,Zeng Lieguang.Analysis and Improvement of High-speed SDH Frame Alignment.Communication Technology Proceedings,IEEE.2000,8
[7] Nazir Al-Subbagh.M,Jones.E.V.Optimum patterns for frame alignment.Radar and Signal Processing.1998,12
[8] D.Bajic,V.Senk,M.Despotovic.Subsets of the STM-1 frame-alignment signal: a monitoring analysis.Communications,IEE.2002,12
[9] Mercury Programmable Logic Device Family.Data Sheet.Altera Corporation.2002,2
[10] Stratix Programmable Logic Device Family.Data Sheet.Altera Corporation.2002,2
[11] Clifford E.Cummings.Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Design.SNUG(Synopsys Users Group).2001
[12] Clifford E.Cummings,Don Mills.Synchronous Resets? Asynchronous Resets?.SNUG(Synopsys Users Group).2002
[13] 王晓明,王志功,黄颋等.甚短距离光传输技术.东南大学学报,Vol.33 No.3,2003,5
[14] 沙燕萍,曾烈光.高速SDH帧同步系统性能与同步码组选择.光通信研究,2000第二期
[15] 岩小平,叶培大.光同步数字系列帧同步性能分析.北京邮电大学学报.第19卷第2期.1996,6
[16] 何颖,屈万里,罗杰.SDH系统帧同步的研究与ASIC实现.半导体技术.第27卷第3期.2002,3
[17] 束礼宝,宋克拄,王砚方.伪随机数发生器的FPGA实现与研究.电路与系统学报.2003,6
[18] 周师亮.伪随机序列原理.电视技术.1997,6
[19] 孙玉.数字复接技术[M].第二版.北京:人民邮电出版社,1991,10
[20] 褚振勇,翁木云.FPGA设计及应用[M].西安:西安电子科技大学出版社.2002,7
[21] 曹志刚,钱亚生.现代通信原理[M].北京:清华大学出版社.1998,10
[22] Donald E.Thomas,Philip R.Morrby著.硬件描述语言Verilog(第四版)[M].刘明业等译.北京:清华大学出版社.2001,8
[23] 张亮.数字电路设计与Verilog HDL[M].北京:人民邮电出版社.2000,10
[24] www.altera.com
[2] ITU-T Recommendation G.783.Characteristics of synchronous digital hierarchy (SDH) equipment functional blocks.1997
[3] M.S.Obaidat,J.Teng.A methodology to analyze the performance of a parallel frame synchronization scheme in SDH high speed networks.Computer Communications 22.1999
[4] Jun Teng,Lei-min Li,M.S.Obaidat.155.52 Mbit/s parallel frame synchronous scheme for SDH networks.Computers and Communications,Conference Proceedings of the 1996 IEEE Fifteenth Annual International Phoenix Conference.1996,3
[5] D.Bajic,J.Stojanovic.Frame-Alignment Monitoring For STM-1 Frame.Communications,IEEE.2001,6
[6] Sha Yanping,Wang Hansheng,Zeng Lieguang.Analysis and Improvement of High-speed SDH Frame Alignment.Communication Technology Proceedings,IEEE.2000,8
[7] Nazir Al-Subbagh.M,Jones.E.V.Optimum patterns for frame alignment.Radar and Signal Processing.1998,12
[8] D.Bajic,V.Senk,M.Despotovic.Subsets of the STM-1 frame-alignment signal: a monitoring analysis.Communications,IEE.2002,12
[9] Mercury Programmable Logic Device Family.Data Sheet.Altera Corporation.2002,2
[10] Stratix Programmable Logic Device Family.Data Sheet.Altera Corporation.2002,2
[11] Clifford E.Cummings.Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Design.SNUG(Synopsys Users Group).2001
[12] Clifford E.Cummings,Don Mills.Synchronous Resets? Asynchronous Resets?.SNUG(Synopsys Users Group).2002
[13] 王晓明,王志功,黄颋等.甚短距离光传输技术.东南大学学报,Vol.33 No.3,2003,5
[14] 沙燕萍,曾烈光.高速SDH帧同步系统性能与同步码组选择.光通信研究,2000第二期
[15] 岩小平,叶培大.光同步数字系列帧同步性能分析.北京邮电大学学报.第19卷第2期.1996,6
[16] 何颖,屈万里,罗杰.SDH系统帧同步的研究与ASIC实现.半导体技术.第27卷第3期.2002,3
[17] 束礼宝,宋克拄,王砚方.伪随机数发生器的FPGA实现与研究.电路与系统学报.2003,6
[18] 周师亮.伪随机序列原理.电视技术.1997,6
[19] 孙玉.数字复接技术[M].第二版.北京:人民邮电出版社,1991,10
[20] 褚振勇,翁木云.FPGA设计及应用[M].西安:西安电子科技大学出版社.2002,7
[21] 曹志刚,钱亚生.现代通信原理[M].北京:清华大学出版社.1998,10
[22] Donald E.Thomas,Philip R.Morrby著.硬件描述语言Verilog(第四版)[M].刘明业等译.北京:清华大学出版社.2001,8
[23] 张亮.数字电路设计与Verilog HDL[M].北京:人民邮电出版社.2000,10
[24] www.altera.com