MEMS三维堆叠模块化封装研究
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摘要
随着MEMS和无线传感技术的发展，对封装密度、集成度、性能和可靠性等提出了更高的要求。三维堆叠模块化封装技术可以将电子、流体、光学等器件集成在一个模块里，实现MEMS／IC、数字／模拟器件的混合组装。垂直互连技术是三维堆叠模块化封装互连的关键性技术。本文提出了一种基于凸点垂直互连技术的新颖的三维堆叠模块化封装结构并对其制备和可靠性进行了研究。
新设计的封装结构是一种将加速度计芯片及调制解调电路集成于三层堆叠模块。采用了顶层模块、框架模块和底层模块的三层堆叠模块结构，主要工艺步骤为：一、对单层模块进行贴片、引线键合和包封；二、印刷焊膏，贴装无源元件；三、用一种新型的垂直定位装置进行定位和回流焊。本文详细阐述了每个实验步骤的具体过程，并通过显微镜、X-ray、Keithley 4500 QIVC等仪器对每个阶段的实验结果进行了观察和分析，并对设计参数进行了优化。
该结构成功的把MEMS器件与IC芯片混合组装在同一模块里；采用了定位销／孔的定位方式，可同时进行3×3个模块的高精度堆叠定位(其对位误差约0.068mm)；通过丝网印刷焊膏，一次回流焊接完成堆叠模块的垂直互连；对模块进行的剪切力测试表明采用印刷焊膏回流实现垂直互连的强度满足相关标准(MIL-STD-883E)；封装体积小(整个加速度计调制解调系统封装后的体积为19×19×8mm~3)；对项层模块与底层模块之间的垂直互连的电性能进行了测量，垂直互连电阻在0.01Ω-0.03Ω之间；最后采用热循环实验对该结构的可靠性进行了测试，结果发现热循环对该封装结构的电性能没有重大影响。
本工作主要在工艺方面实现了该封装结构，为进一步的实用化奠定了基础。
The trend towards miniaturization, multifunction, autonomous and smart systems in different application fields (IT, wireless communication, computing, mobiles, etc) is prevailing in electronic packaging industry. 3D packaging technologies are developing necessarily to fulfill the application requirements.
3D packaging technologies are normally divided into three types: embedded, active substrate, stacked. The problems in the embedded 3D packaging technology are low precision of embedded passive components and yield of embedded active components; the active substrate 3D packaging technology has the problem of low yield of active silicon substrate. On the other hand, the stacked 3D packaging technology is compatible with traditional assembly and packaging technologies (SMT, COB, FCOB, etc), and the vertical interconnection technology could reduce the propagation delay, power consumption, and noise. The stacked naked devices or package in level 1 can not be satisfied to the requirements of higher density and larger integrated level. Therefore, stacked MCM—3D stacked module packaging is preferable in terms of low cost, high density and yield.
In this paper, a new 3D stacked module packaging technology with a novel alignment tool of vertical interconnection was developed to meet the general requirements of MEMS and wireless communication packaging such as high density, low cost and high yield. According to the requirements of modular package, three layers of the stacked module were designed and fabricated on the basis of an accelerometer's modem circuit. By stencil printing, passive devices" attaching, aligning by an alignment tool of vertical interconnection and reflowing, a 3D stacked modular package structure of an accelerometer's modem circuit was successfully manufactured. MEMS and IC devices were assembled in the same module, high Precision (the alignment error was about 0.068 mm) stacked alignment of 3×3 modules was completed by the method of alignment bar/via, The vertical interconnection of the stacked module was achieved by stencil printing and reflowing, the average strength of solder joints was above 22.3MPa, the volume of the entire stacked module was about 19×19×8 mm~3. Influencing factors on the vertical interconnection were discussed and shear strength test of the module was presented.
新设计的封装结构是一种将加速度计芯片及调制解调电路集成于三层堆叠模块。采用了顶层模块、框架模块和底层模块的三层堆叠模块结构，主要工艺步骤为：一、对单层模块进行贴片、引线键合和包封；二、印刷焊膏，贴装无源元件；三、用一种新型的垂直定位装置进行定位和回流焊。本文详细阐述了每个实验步骤的具体过程，并通过显微镜、X-ray、Keithley 4500 QIVC等仪器对每个阶段的实验结果进行了观察和分析，并对设计参数进行了优化。
该结构成功的把MEMS器件与IC芯片混合组装在同一模块里；采用了定位销／孔的定位方式，可同时进行3×3个模块的高精度堆叠定位(其对位误差约0.068mm)；通过丝网印刷焊膏，一次回流焊接完成堆叠模块的垂直互连；对模块进行的剪切力测试表明采用印刷焊膏回流实现垂直互连的强度满足相关标准(MIL-STD-883E)；封装体积小(整个加速度计调制解调系统封装后的体积为19×19×8mm~3)；对项层模块与底层模块之间的垂直互连的电性能进行了测量，垂直互连电阻在0.01Ω-0.03Ω之间；最后采用热循环实验对该结构的可靠性进行了测试，结果发现热循环对该封装结构的电性能没有重大影响。
本工作主要在工艺方面实现了该封装结构，为进一步的实用化奠定了基础。
The trend towards miniaturization, multifunction, autonomous and smart systems in different application fields (IT, wireless communication, computing, mobiles, etc) is prevailing in electronic packaging industry. 3D packaging technologies are developing necessarily to fulfill the application requirements.
3D packaging technologies are normally divided into three types: embedded, active substrate, stacked. The problems in the embedded 3D packaging technology are low precision of embedded passive components and yield of embedded active components; the active substrate 3D packaging technology has the problem of low yield of active silicon substrate. On the other hand, the stacked 3D packaging technology is compatible with traditional assembly and packaging technologies (SMT, COB, FCOB, etc), and the vertical interconnection technology could reduce the propagation delay, power consumption, and noise. The stacked naked devices or package in level 1 can not be satisfied to the requirements of higher density and larger integrated level. Therefore, stacked MCM—3D stacked module packaging is preferable in terms of low cost, high density and yield.
In this paper, a new 3D stacked module packaging technology with a novel alignment tool of vertical interconnection was developed to meet the general requirements of MEMS and wireless communication packaging such as high density, low cost and high yield. According to the requirements of modular package, three layers of the stacked module were designed and fabricated on the basis of an accelerometer's modem circuit. By stencil printing, passive devices" attaching, aligning by an alignment tool of vertical interconnection and reflowing, a 3D stacked modular package structure of an accelerometer's modem circuit was successfully manufactured. MEMS and IC devices were assembled in the same module, high Precision (the alignment error was about 0.068 mm) stacked alignment of 3×3 modules was completed by the method of alignment bar/via, The vertical interconnection of the stacked module was achieved by stencil printing and reflowing, the average strength of solder joints was above 22.3MPa, the volume of the entire stacked module was about 19×19×8 mm~3. Influencing factors on the vertical interconnection were discussed and shear strength test of the module was presented.
引文
[1] Said F. Al-sarawi, Derek Abbott, Paul D. Franzon. A Review of 3-D Packaging Technology. IEEE Transactions on Components, Packaging, and Manufacturing-PART B, Vol. 21, No. 1, February 1998
[2] 杨建生．BGA多芯片组件及三维立体封装(3D)技术．电子与封装，第三卷，第一期．
[3] Mark Klossner, Steve Babinetz. Assembly Solutions for 3-D Stacked Devices. SEMICON Singapore, 2002, ppA1-A10
[4] Yasuki Fukui, Yuji Yano, et al. Triple-Chip Stacked CSP. Electronic Components and Technology Conference, 2000, pp385-389
[5] Dreiza Moody, Smith Lee, et al. "Stacked Package on Package (PoP) Design Guidelines", International Wafer Level Packaging Congress, San Jose, CA November 2005
[6] Flynn Carson, Young-Cheol Kim. The Development of a Novel Stacked Package: Package in Package. Electronics Manufacturing Technology Symposium, 2004. IEEE/CPMT/SEMI 29th International Jul 14-16, 2004, pp91-96
[7] Moody Dreiza, Lee Smith, et al. Package on Package (PoP) Stacking and Board Level Reliability, Results of Joint Industry Study
[8] Joseph Y. Lee, Jinyong Ahn, et al. Package on Package(PoP)for Advanced PCB Manufacturing Process. 2006 7th International Conference on Electronics Packaging Technology
[9] Rudolf Leutenbauer, Volker Grosset, Bernd Michel, et al. The Development of a Top-Bottom-BGA(TB-BGA). Electronic Components and Technology Conference, 1998, pp1235-1240
[10] Schuenemann M., Jam K. A., et al. MEMS Modular Packaging and Interfaces Electronic Components and Technology Conference, 2000. 2000 Proceedings. 50th 21-24 May 2000, pp681-688
[11] Pienimaa S. K., Miettinen J., et al. Stacked Modular Package. Advanced Packaging, IEEE Transactions on [see also Components, Packaging and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on] Volume 27, Issue 3, Aug. 2004, pp461-466
[12] Kourosh Amiri Jam, Volker Groβer, Klaus-Dieter Lang, et al. Application of 3D-Stacking Technology for Sensor Integration and Miniaturization. Micro System Technologies 2005, 2005. 10, pp05-06
[13] Dipl. -Ing. Kourosh Amiri Jam, et al. Design, fabrication and test of electrical modules with several assembly layers. Micro-tec2003, 2003. 10: 13-15.
[14] Kourosh Amiri Jam, Volker Groβer, Klaus-Dieter Lang, et al. Application of 3D-Stacking Technology for Sensor Integration and Miniaturization. Micro System Technologies 2005, 2005. 10, pp05-06
[15] Takao Yamazaki, Yoshimichi Sogawa, et al. Real Chip Size Three-Dimensional Stackde Package. IEEE Transactions on Advanced Packaging, Vol. 27, No. 3, August 2005
[16] A. Bossche, et al. MEMS packaging: State of the art and future trends, SPIE Vol. 3328, pp166-173
[17] 凌科，全球微机电系统市场新轨迹，电子产品世界，1999年9月
[18] 李宝清，陆德仁，王渭源．高线性微机械差分电容式加速度计测量电路．测控技术，1999 年18卷第10期
[19] J.A. Minahan, A.Pepe, et al. The 3-D stack in short form(memory chip packaging). In proc. 1992 42nd Electron. Comp. Technol. Conf., San Diego, CA, May 1992
[20] M. Coello-Vera, A. Masgrangeas, C. Val, and M. Leroy, "'256 Mbits MCM-V memory stack," in Proc. 1995 Int. Conf. Multichip Modules, Denver, CO, Apr. 1995, pp 24-29
[21] C. Cahill, A. Compagno, et al. Thermal characterization of vertical multichip modules MCM-V. Components, Packaging, and Manufacturing Technology, Part A, IEEE Transactions on [see also Components, Hybrids, and Manufacturing Technology, IEEE Transactions on], vol. 18, Dec. 1995, pp765-772
[22] Wojciechowski D., Vanfletern J., et al. Electro - conductive adhesives for high density package and flip - chip interconnections [J] .Microelectronics Reliability ,2000,40, pp1215 - 1226
[23] Myung Jin Yim, Kyung Wook Paik. Recent advances on anisotropic conductive adhesives (ACAs) for flat panel displays and semiconductor packaging applications. International Journal of Adhesion and Adhesives, Volume 26, Issue 5, August 2006, pp304-313
[24] Jean-Charles Sourian, Cyrille Rossat. Electronical conductive film for Flip chip interconnection based on Z- axis conductors [C]. Electronic components and technology conference, 2002, pp1151 - 1153
[25] 蔺永诚，陈旭．各向异性导电胶互连技术的研究进展．电子与封装，Vol 6，No．7
[26] M. Massenat. High-density package, cofired, multi-chip module, 3-D,a mass memory mixed technology for space applications," in Proc. 9th Eur. Hybrid Microelectron. Conf., Nice, France, June 1993, pp216-223
[27] D. B. Tuckerman, L.-O. Bauer, et al. Laminated memory: A new 3-dimensional packaging technology for MCM's. in Proc. 1994 IEEE Multi-Chip Module Conf. MCMC-94, IEEE Comput. Soc. Press, Santa Cruz, CA, Mar. 1994, pp58-63
[28] G. Rochat. COB and COC for low cost and high density package, in Proc. 17th IEEE/CPMT Int. Electron. Manufact. Technol. Syrup. "Manufact. Technol.-Present and Future," Austin, TX, Oct. 1995, pp109—111
[29] Stephen Babinetz, James Loftin, et al. looping challenges in next generation packaging. Semicon Singapore 2001
[30] Paul Reid, Ivy Wei Qin, et al. Providing Stacked Die Solutions with Wedge Bonding Technology. Semicon Singapore 2002
[31] Ivy Wei Qin, Paul Bereznycky, et al. wedge bonding for ultra fine pitch applications [J]. Kulicke & Soffa, 2003, 2(1), ppA1 -AI0
[32] Manfred Boheim, Uhland Goebel. Low Cost Packages for Micro- and Millimeterwave Circuits. European Microwave Conference, 1994.24th, Publication Date: Oct. 1994, Volume: 1, pp122-132
[33] S.E. Greer. An Extended Eutectic Solder Bump for FCOB. ECTC 1996 Proceedings
[34] Chul-Won Ju, Seong-Jin Kim, et al. The Effect of Via Size on Fine Pitch and High Density Solder Bumps for Wafer Level Packaging.2002 Electronic Components and Technology Conference, ppl 178-1181
[35] Fumitaka Ueno, Tomohisa Motomura, et al. new flip chip attach technology for fine pitch interconnections using electroplated copper bumps formed on a substrate. 1998 IEMT/IMC Proceedings, pp354-368
[36] S.Lee, Y.X.Guo, et al. Electro-migration Effect on Cu-pillar (Sn) Bumps.2005 Electronics Packaging Technology Conference, ppl35-139
[37] Rick Yu, Jui-I Yu, et al. Process Characteristics of 100um Bump pitch with Lead-Free and High Lead Plating Solder Bump. 2005 Electronics Packaging Technology Conference, pp497-502
[38] J. Simon, E. Zakel, et al. Electroless Deposition of Bumps for TAB Technology. Electronic Components and Technology Conference, 1990. Proceedings., 40th 20-23 May 1990, vol.1, pp412 -417
[39] W. Reinert, T. Harder. Performance of the Stud Bump Bonding (SBB) Process in Comparison to Solder Flip Chip Technology. 2000 IEEE, ppl36-140
[40] M. Klein, E. Busse, et al. Investigation of Cu Stud Bumping for Single Chip Flip-Chip Assembly. 2004 Electronic Components and Technology Conference, pp 1181-1186
[41] Suwa Motoo et al, Development of a New Flip-Chip Bonding Process Using Multi-Stacked- Au Bumps, Proceedings of the Electronic Components and Technology Conference, Washington, DC, May 1-4, 1994. pp906-909
[42] Metzger D., Beutler U., et al. Laser bumping for flip chip and TAB applications. Electronic Components and Technology Conference, 1994. Proceedings., 44th, 1-4 May 1994, pp910-916
[43] Eric Laine, Klaus Ruhmer, et al. C4NP as a High-Volume Manufacturing Method for Fine-Pitch and Lead-Free Flip Chip Solder Bumping. 2006 Electronics System integration Technology Conference, Dresden, Germany, pp518-524
[44] Hotchkiss G. Tachy dotsTM transfer of solder spheres for flip chip and electronic package applications[C].Electronic com2ponents and technology conference, 1998, pp434-441
[45] F.Ansorge. K.-F.Becker, et al. Recent Progress in Flexible Molding and Reliability Investigation of CSP and BGA-Packages using advanced Interconnection Technology. 1997 IEEE, pp14-22
[46] P. Kasulke, G Azdasht, et al. A New Solution For Solder Application To FCA, BGA, and CSP Challenges. Proc. Micro Systems Technology, 1996
[47] Hashino E , Shimokawa K. Micro-ball wafer bumping for flip chip interconnection [C].2001 Electronic Components and Technology Conference ,2001
[48] Jong-Kai Lin, Treliant Fang, et al. Squeegee Bump Technology. IEEE Transactions on Components, Packaging, and Manufacturing, Vol.25, No. 1, March 2002, pp 38-44
[49] Y. M.Chow,W. M.Lau, Feasibility And Reliability Study On The Electroless Nickel Bumping And Stencil Solder Printing For Low-cost Flip Chip Electronic Packaging. Electronic Materials & Packaging, 2000, pp79-85
[50] Heilmann, N. A comparison of vapor-phase, infrared and hot-gas soldering. Electronic Manufacturing Technology Symposium, 1988, Fourth IEEE/CHMT European International 13-15 June 1988, pp70-72
[51] MIL-STD-883E, method 2019.5
[52] MIL-STD-883E, method 2011.7
[2] 杨建生．BGA多芯片组件及三维立体封装(3D)技术．电子与封装，第三卷，第一期．
[3] Mark Klossner, Steve Babinetz. Assembly Solutions for 3-D Stacked Devices. SEMICON Singapore, 2002, ppA1-A10
[4] Yasuki Fukui, Yuji Yano, et al. Triple-Chip Stacked CSP. Electronic Components and Technology Conference, 2000, pp385-389
[5] Dreiza Moody, Smith Lee, et al. "Stacked Package on Package (PoP) Design Guidelines", International Wafer Level Packaging Congress, San Jose, CA November 2005
[6] Flynn Carson, Young-Cheol Kim. The Development of a Novel Stacked Package: Package in Package. Electronics Manufacturing Technology Symposium, 2004. IEEE/CPMT/SEMI 29th International Jul 14-16, 2004, pp91-96
[7] Moody Dreiza, Lee Smith, et al. Package on Package (PoP) Stacking and Board Level Reliability, Results of Joint Industry Study
[8] Joseph Y. Lee, Jinyong Ahn, et al. Package on Package(PoP)for Advanced PCB Manufacturing Process. 2006 7th International Conference on Electronics Packaging Technology
[9] Rudolf Leutenbauer, Volker Grosset, Bernd Michel, et al. The Development of a Top-Bottom-BGA(TB-BGA). Electronic Components and Technology Conference, 1998, pp1235-1240
[10] Schuenemann M., Jam K. A., et al. MEMS Modular Packaging and Interfaces Electronic Components and Technology Conference, 2000. 2000 Proceedings. 50th 21-24 May 2000, pp681-688
[11] Pienimaa S. K., Miettinen J., et al. Stacked Modular Package. Advanced Packaging, IEEE Transactions on [see also Components, Packaging and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on] Volume 27, Issue 3, Aug. 2004, pp461-466
[12] Kourosh Amiri Jam, Volker Groβer, Klaus-Dieter Lang, et al. Application of 3D-Stacking Technology for Sensor Integration and Miniaturization. Micro System Technologies 2005, 2005. 10, pp05-06
[13] Dipl. -Ing. Kourosh Amiri Jam, et al. Design, fabrication and test of electrical modules with several assembly layers. Micro-tec2003, 2003. 10: 13-15.
[14] Kourosh Amiri Jam, Volker Groβer, Klaus-Dieter Lang, et al. Application of 3D-Stacking Technology for Sensor Integration and Miniaturization. Micro System Technologies 2005, 2005. 10, pp05-06
[15] Takao Yamazaki, Yoshimichi Sogawa, et al. Real Chip Size Three-Dimensional Stackde Package. IEEE Transactions on Advanced Packaging, Vol. 27, No. 3, August 2005
[16] A. Bossche, et al. MEMS packaging: State of the art and future trends, SPIE Vol. 3328, pp166-173
[17] 凌科，全球微机电系统市场新轨迹，电子产品世界，1999年9月
[18] 李宝清，陆德仁，王渭源．高线性微机械差分电容式加速度计测量电路．测控技术，1999 年18卷第10期
[19] J.A. Minahan, A.Pepe, et al. The 3-D stack in short form(memory chip packaging). In proc. 1992 42nd Electron. Comp. Technol. Conf., San Diego, CA, May 1992
[20] M. Coello-Vera, A. Masgrangeas, C. Val, and M. Leroy, "'256 Mbits MCM-V memory stack," in Proc. 1995 Int. Conf. Multichip Modules, Denver, CO, Apr. 1995, pp 24-29
[21] C. Cahill, A. Compagno, et al. Thermal characterization of vertical multichip modules MCM-V. Components, Packaging, and Manufacturing Technology, Part A, IEEE Transactions on [see also Components, Hybrids, and Manufacturing Technology, IEEE Transactions on], vol. 18, Dec. 1995, pp765-772
[22] Wojciechowski D., Vanfletern J., et al. Electro - conductive adhesives for high density package and flip - chip interconnections [J] .Microelectronics Reliability ,2000,40, pp1215 - 1226
[23] Myung Jin Yim, Kyung Wook Paik. Recent advances on anisotropic conductive adhesives (ACAs) for flat panel displays and semiconductor packaging applications. International Journal of Adhesion and Adhesives, Volume 26, Issue 5, August 2006, pp304-313
[24] Jean-Charles Sourian, Cyrille Rossat. Electronical conductive film for Flip chip interconnection based on Z- axis conductors [C]. Electronic components and technology conference, 2002, pp1151 - 1153
[25] 蔺永诚，陈旭．各向异性导电胶互连技术的研究进展．电子与封装，Vol 6，No．7
[26] M. Massenat. High-density package, cofired, multi-chip module, 3-D,a mass memory mixed technology for space applications," in Proc. 9th Eur. Hybrid Microelectron. Conf., Nice, France, June 1993, pp216-223
[27] D. B. Tuckerman, L.-O. Bauer, et al. Laminated memory: A new 3-dimensional packaging technology for MCM's. in Proc. 1994 IEEE Multi-Chip Module Conf. MCMC-94, IEEE Comput. Soc. Press, Santa Cruz, CA, Mar. 1994, pp58-63
[28] G. Rochat. COB and COC for low cost and high density package, in Proc. 17th IEEE/CPMT Int. Electron. Manufact. Technol. Syrup. "Manufact. Technol.-Present and Future," Austin, TX, Oct. 1995, pp109—111
[29] Stephen Babinetz, James Loftin, et al. looping challenges in next generation packaging. Semicon Singapore 2001
[30] Paul Reid, Ivy Wei Qin, et al. Providing Stacked Die Solutions with Wedge Bonding Technology. Semicon Singapore 2002
[31] Ivy Wei Qin, Paul Bereznycky, et al. wedge bonding for ultra fine pitch applications [J]. Kulicke & Soffa, 2003, 2(1), ppA1 -AI0
[32] Manfred Boheim, Uhland Goebel. Low Cost Packages for Micro- and Millimeterwave Circuits. European Microwave Conference, 1994.24th, Publication Date: Oct. 1994, Volume: 1, pp122-132
[33] S.E. Greer. An Extended Eutectic Solder Bump for FCOB. ECTC 1996 Proceedings
[34] Chul-Won Ju, Seong-Jin Kim, et al. The Effect of Via Size on Fine Pitch and High Density Solder Bumps for Wafer Level Packaging.2002 Electronic Components and Technology Conference, ppl 178-1181
[35] Fumitaka Ueno, Tomohisa Motomura, et al. new flip chip attach technology for fine pitch interconnections using electroplated copper bumps formed on a substrate. 1998 IEMT/IMC Proceedings, pp354-368
[36] S.Lee, Y.X.Guo, et al. Electro-migration Effect on Cu-pillar (Sn) Bumps.2005 Electronics Packaging Technology Conference, ppl35-139
[37] Rick Yu, Jui-I Yu, et al. Process Characteristics of 100um Bump pitch with Lead-Free and High Lead Plating Solder Bump. 2005 Electronics Packaging Technology Conference, pp497-502
[38] J. Simon, E. Zakel, et al. Electroless Deposition of Bumps for TAB Technology. Electronic Components and Technology Conference, 1990. Proceedings., 40th 20-23 May 1990, vol.1, pp412 -417
[39] W. Reinert, T. Harder. Performance of the Stud Bump Bonding (SBB) Process in Comparison to Solder Flip Chip Technology. 2000 IEEE, ppl36-140
[40] M. Klein, E. Busse, et al. Investigation of Cu Stud Bumping for Single Chip Flip-Chip Assembly. 2004 Electronic Components and Technology Conference, pp 1181-1186
[41] Suwa Motoo et al, Development of a New Flip-Chip Bonding Process Using Multi-Stacked- Au Bumps, Proceedings of the Electronic Components and Technology Conference, Washington, DC, May 1-4, 1994. pp906-909
[42] Metzger D., Beutler U., et al. Laser bumping for flip chip and TAB applications. Electronic Components and Technology Conference, 1994. Proceedings., 44th, 1-4 May 1994, pp910-916
[43] Eric Laine, Klaus Ruhmer, et al. C4NP as a High-Volume Manufacturing Method for Fine-Pitch and Lead-Free Flip Chip Solder Bumping. 2006 Electronics System integration Technology Conference, Dresden, Germany, pp518-524
[44] Hotchkiss G. Tachy dotsTM transfer of solder spheres for flip chip and electronic package applications[C].Electronic com2ponents and technology conference, 1998, pp434-441
[45] F.Ansorge. K.-F.Becker, et al. Recent Progress in Flexible Molding and Reliability Investigation of CSP and BGA-Packages using advanced Interconnection Technology. 1997 IEEE, pp14-22
[46] P. Kasulke, G Azdasht, et al. A New Solution For Solder Application To FCA, BGA, and CSP Challenges. Proc. Micro Systems Technology, 1996
[47] Hashino E , Shimokawa K. Micro-ball wafer bumping for flip chip interconnection [C].2001 Electronic Components and Technology Conference ,2001
[48] Jong-Kai Lin, Treliant Fang, et al. Squeegee Bump Technology. IEEE Transactions on Components, Packaging, and Manufacturing, Vol.25, No. 1, March 2002, pp 38-44
[49] Y. M.Chow,W. M.Lau, Feasibility And Reliability Study On The Electroless Nickel Bumping And Stencil Solder Printing For Low-cost Flip Chip Electronic Packaging. Electronic Materials & Packaging, 2000, pp79-85
[50] Heilmann, N. A comparison of vapor-phase, infrared and hot-gas soldering. Electronic Manufacturing Technology Symposium, 1988, Fourth IEEE/CHMT European International 13-15 June 1988, pp70-72
[51] MIL-STD-883E, method 2019.5
[52] MIL-STD-883E, method 2011.7