面向数字系统的确定性自测试与延迟故障测试
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摘要
集成电路测试是微电子领域中一个日益重要的问题。可测性设计尽可能早的在集成电路设计时考虑测试问题。内建自测试设计(BIST)是可测性设计的一种重要方法。本论文对数字系统基于扫描的BIST技术进行了深入研究。路径延迟故障测试能够检测到针对固定型故障的测试向量所无法检测到的缺陷。我们针对路径延迟故障的故障模拟问题也进行了深入的研究。
论文提出了一个基于扫描森林结构和加权扫描选通信号的自测试策略,来获得针对单固定型故障的100%故障覆盖率。这一自测试策略包含伪随机测试阶段和确定性测试阶段。一个新的测度被提出以获得具有较少的确定位数量的确定性测试向量。对于所有的实验电路,通过使用级数为确定性测试向量的确定位数量最大值的线性反馈移位寄存器,本策略可以编码所有的确定性测试向量。
论文提出了一个针对路径延迟故障的快速并精确的故障模拟器。这一故障模拟器基于robustly testable路径集和non-robustly testable路径集构造选择路径电路。故障模拟被简化为在原始电路上的逻辑模拟。通过有效的修剪选择路径电路,我们提出了一个基于选择性后向追踪策略的故障抛弃技术。同时,修剪过程提高了故障模拟的速度,并保证故障模拟的精确性。
The testing of integrated circuits is an emerging issue in Microelectronics. DFT (design for testability) method tries to resolve the test problem in the early process of IC design. BIST (built-in self-test) is an important DFT technique. In this thesis, we research on scan-based BIST techniques of digital systems. Path delay fault testing can detect lots of defects that can not be detected by the test patterns targeting stuck-at faults. We also research on the fault simulation of path delay fault.
A scan-based BIST scheme based on the scan-forest architecture and weighted scan-enable signals is proposed to acquire complete fault coverage of single stuck-at faults. The proposed BIST scheme relies on a pseudo-random testing phase and a deterministic phase. A new testability measure is presented to guide test generation such that test patterns with fewer care bits are obtained. For all benchmark circuits, the method is able to encode all deterministic test patterns using an LFSR whose size is equal to the maximum number of care bits in a test pattern.
A fast and exact fault simulator is proposed for path delay faults. The proposed fault simulator constructs SPC (selected path circuit) based on non-robustly testable or robustly testable path set. Fault simulation is reduced to logic simulation on the original circuit. By effectively pruning the SPC, we propose an effective fault dropping technique with a backward selective tracing scheme. Additionally, the pruning process raises the speed of fault simulation, while assures the exactness of fault simulation.
论文提出了一个基于扫描森林结构和加权扫描选通信号的自测试策略,来获得针对单固定型故障的100%故障覆盖率。这一自测试策略包含伪随机测试阶段和确定性测试阶段。一个新的测度被提出以获得具有较少的确定位数量的确定性测试向量。对于所有的实验电路,通过使用级数为确定性测试向量的确定位数量最大值的线性反馈移位寄存器,本策略可以编码所有的确定性测试向量。
论文提出了一个针对路径延迟故障的快速并精确的故障模拟器。这一故障模拟器基于robustly testable路径集和non-robustly testable路径集构造选择路径电路。故障模拟被简化为在原始电路上的逻辑模拟。通过有效的修剪选择路径电路,我们提出了一个基于选择性后向追踪策略的故障抛弃技术。同时,修剪过程提高了故障模拟的速度,并保证故障模拟的精确性。
The testing of integrated circuits is an emerging issue in Microelectronics. DFT (design for testability) method tries to resolve the test problem in the early process of IC design. BIST (built-in self-test) is an important DFT technique. In this thesis, we research on scan-based BIST techniques of digital systems. Path delay fault testing can detect lots of defects that can not be detected by the test patterns targeting stuck-at faults. We also research on the fault simulation of path delay fault.
A scan-based BIST scheme based on the scan-forest architecture and weighted scan-enable signals is proposed to acquire complete fault coverage of single stuck-at faults. The proposed BIST scheme relies on a pseudo-random testing phase and a deterministic phase. A new testability measure is presented to guide test generation such that test patterns with fewer care bits are obtained. For all benchmark circuits, the method is able to encode all deterministic test patterns using an LFSR whose size is equal to the maximum number of care bits in a test pattern.
A fast and exact fault simulator is proposed for path delay faults. The proposed fault simulator constructs SPC (selected path circuit) based on non-robustly testable or robustly testable path set. Fault simulation is reduced to logic simulation on the original circuit. By effectively pruning the SPC, we propose an effective fault dropping technique with a backward selective tracing scheme. Additionally, the pruning process raises the speed of fault simulation, while assures the exactness of fault simulation.
引文
[1] 向东,数字系统测试及可测试性设计。北京,科学出版社,1997。
[2] 徐奕,同步时序电路的非扫描可测试性设计:[硕士学位论文]。北京:清华大学微电子研究所,2001。
[3] 顾珊,具有低测试代价的同步时序电路可测试性设计技术:[硕士学位论文]。北京:清华大学微电子研究所,2002。
[4] 陈明静,面向数字系统的基于扫描的内建自测试新技术:[硕士学位论文]。北京:清华大学微电子研究所,2005。
[5] 李开伟,低成本高效率的扫描测试:[硕士学位论文]。北京:清华大学计算机科学与技术系,2006。
[6] M. A. Gharaybeh, M. L. Bushnell, and V. D. Agrawal, “An exact non-enumerative fault simulation for path delay faults,” Proc. of ITC, pp. 276-285, 1996.
[7] D. Kagaris and S. Tragoudas, “On the non-enumerative fault simulation problems,” IEEE Trans. on CAD, vol. 21, no. 9, pp. 1095-1101, 2002.
[8] S. Padmanaban and S. Tragoudas, “Efficient identification of (critical) testable path delay faults using decision diagrams,” IEEE Trans. On CAD, vol. 24, no. 1, pp. 77-87, 2005.
[9] D. Xiang, K. Li, H. Fujiwara, and J. Sun, “Generating compact robust and non-robust tests for complete coverage of path delay faults based on stuck-at tests,” Proc. of ICCD, pp. 446-451, 2006.
[10] P. H. Bardell, W. H. McAnney, and J. Savir, Built-in Test for VLSI: Pseudo-Random Techniques, NewYork: Wiley, 1987.
[11] I. Pomeranz and S. M. Reddy, “3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits,” IEEE Trans. on CAD, vol. 24, no. 7, pp. 1050-1058, 1993.
[12] Y. Huang, I. Pomeranz, S. M. Reddy, and J. Rajski, “Improving the property of at-speed tests,” Proc. of IEEE/ACM Int. Conf. CAD, pp. 459-463, 2000.
[13] H. C. Tsai, K. T. Cheng, and S. Bhawmik, “On improving test quality of scan-based BIST,” IEEE Trans. on CAD, vol. 19, no. 8, pp. 928-938, 2000.
[14] D. Xiang, M. J. Chen, J. G. Sun, and H. Fujiwara, “Improving test effectiveness of scan-based BIST using scan chain partitioning,” IEEE Trans. on CAD, vol. 24, no. 6, pp. 916-927, 2005.
[15] B. Koenemann, “LFSR-coded test patterns for scan designs,” Proc. of ETS, pp. 237-242, 1991.
[16] B. Koenemann, C. Barnhart, B. Keller, T. Snethen, O. Farnsworth, and D. Wheater, “A smart BIST variant with guaranteed encoding,” Proc. of IEEE ATS, pp. 325-330, 2001.
[17] R. Kapur, S. Patil, T. J. Snethen, and T. W. Williams, “A weighted random pattern testgeneration system,” IEEE Trans. on CAD, vol. 15, pp. 1020-1025, 1996.
[18] A. Jas, C. V. Krishna, and N. A. Touba, “Weighted pseudo-random hybrid BIST,” IEEE Trans. on VLSI Systems, vol. 12, no. 12, pp. 1277-1283, 2004.
[19] G. Kiefer and H. J. Wunderlich, “Deterministic BIST with multiple scan chains,” Proc. of IEEE ITC, pp. 1057-1064, 2000.
[20] J. Rajski, N. Tamarapalli, and J. Tyszer, “Automated synthesis of large phase shifters for built-in self-test ,” Proc. of IEEE ITC, pp. 1047-1056, 1998.
[21] J. Rajski, J. Tyszer, and N. Zacharia, “Test data decompression for multiple scan designs with boundary scan,” IEEE Trans. on Computers, vol. 47, no. 11, pp. 1188-1200, 1998.
[22] S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, and B. Courtois, “Build in test for circuits with scan based on reseeding of multiple polynomial linear feedback shift registers,” IEEE Trans. on Computers, vol. 44, no.2, pp. 223-233, 1995.
[23] S. Hellebrand, B. Reed, S. Tarnick, H.J. Wonderlich, “Pattern generation for a deterministic BIST scheme,” Proc. Of IEEE/ ACM Int. Conference on Computer-Aided Design, pp. 84-95, 1995.
[24] C. V. Krishna, A. Jas, and N. Touba, “Archieving high encoding efficiency with partial dynamic LFSR reseeding,” ACM Trans. on Design Automation of Electronic Systems, vol. 9, no. 4, pp. 500-516, 2004.
[25] H. S. Kim, Y. Kim, and S. Kang, “Test decompression mechanism using a variable multiple polynomial LFSR,” IEEE Trans. on VLSI System, vol. 11, no. 4, pp. 687-690, 2003.
[26] A. A. Al-Yamani, S. Mitra, and E. J. McCluskey, “Optimized reseeding by seed ordering and encoding,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 2, pp. 264-270, 2005.
[27] L. Li and K. Chakrabarty, “Test set embedding for deterministic BIST using a configurable introduction network,” IEEE Trans. on Computers, vol. 23, no. 9, pp. 1289-1305, 2003.
[28] D. Xiang, S. Gu, J. Su, and Y. Wu, “A cost-effective scan architecture for scan testing with non-scan test power and test application cost,” Proc. of ACM/IEEE Design Automation Conference, pp. 744-747, 2003.
[29] M. A. Shah and J. H. Patel, “Enhancement of the Illinois scan architecture for use with multiple scan inputs,” Proc. of Int. Annual Symposium on VLSI, pp. 167-172, 2004.
[30] F. Brglez, “On testability of combinational networks,” Proc. of IEEE Int. Symp. on Circuits and Systems, pp. 221-225, 1984.
[31] S. Ohtake, K. Ohtani, and H. Fujiwara, “A method of test generation for path delay faults using stuck-at fault test generation algorithms,” Proc. of DATE, pp. 310-325, 2003.
[32] H. K. Lee and D. S. Ha, “On the generation of test patterns for combinational circuits,” Technical report 12-93, Dept. of Electrical Eng., Virginia Polytechnic Institute and State University.
[33] T. M. Niermann, “W. T. Cheng, and J. H. Patel,” “PROOFS: A fast memory efficient sequential circuit fault simulator,” IEEE Trans. on CAD, vol. 11, no. 2, pp. 198-207, 1992.
[34] M. A. Shah and J. H. Patel, “Enhancement of the Illinois scan architecture for use withmultiple scan inputs,” Proc. of Int. Annual Symposium on VLSI, pp. 167-172, 2004.
[35] N. Oh, R. Kapur, and T. W. Williams, “Fast seed computation for reseeding shift register in test pattern compression,” Proc. of IEEE/ACM Int. Conference on CAD, pp. 76-81, 2002.
[36] H. K. Lee and D. S. Ha, “HOPE: An efficient parallel fault simulator for synchronous sequential circuits,” IEEE Trans. on CAD, vol. 15, no. 9, pp. 1048-1058, 1996.
[37] I. Pomeranz and S. M. Reddy, “A measure of quality for n-detection test sets,” IEEE Trans. on Computers, vol. 53, no. 11, pp. 1497-1503, 2004.
[38] A. Saldanha, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, “Equivalence of robust delay-fault and single stuck-at fault test generation,” Proc. of DAC, pp. 173-176, 1992.
[39] M. H. Schultz, F. Fink, and K. Fuchs, “Parallel pattern fault simulation of path delay faults,” Proc. of DAC, pp. 357-363, 1989.
[40] I. Pomeranz and S. M. Reddy, “An efficient non-enumerative method to estimate path delay fault coverage,” IEEE Trans. on CAD, vol. 13, no. 2, pp. 240-250, 1994.
[41] Dong Xiang, Yang Zhao, Krishnendu Chakrabarty and Hideo Fujiwara, "Compressing test data for deterministic BIST using a reconfigurable scan architecture," Proc. of the 15th IEEE Asian Test Symposium, pp. 299- 304, 2006.
[42] Yang Zhao, Dong Xiang and Krishnendu Chakrabarty, "Reducing test data volume for deterministic BIST via test-point insertion," accepted as poster presentation in 12th IEEE European Test Symposium, 2007.
[43] D. Xiang, K. Li, J. G. Sun, and H. Fujiwara, “Reconfigured scan forest for test application cost, test data volume, and test power reduction,” IEEE Trans. on Computers, vol. 56, no. 4, pp. 557-562, 2007.
[2] 徐奕,同步时序电路的非扫描可测试性设计:[硕士学位论文]。北京:清华大学微电子研究所,2001。
[3] 顾珊,具有低测试代价的同步时序电路可测试性设计技术:[硕士学位论文]。北京:清华大学微电子研究所,2002。
[4] 陈明静,面向数字系统的基于扫描的内建自测试新技术:[硕士学位论文]。北京:清华大学微电子研究所,2005。
[5] 李开伟,低成本高效率的扫描测试:[硕士学位论文]。北京:清华大学计算机科学与技术系,2006。
[6] M. A. Gharaybeh, M. L. Bushnell, and V. D. Agrawal, “An exact non-enumerative fault simulation for path delay faults,” Proc. of ITC, pp. 276-285, 1996.
[7] D. Kagaris and S. Tragoudas, “On the non-enumerative fault simulation problems,” IEEE Trans. on CAD, vol. 21, no. 9, pp. 1095-1101, 2002.
[8] S. Padmanaban and S. Tragoudas, “Efficient identification of (critical) testable path delay faults using decision diagrams,” IEEE Trans. On CAD, vol. 24, no. 1, pp. 77-87, 2005.
[9] D. Xiang, K. Li, H. Fujiwara, and J. Sun, “Generating compact robust and non-robust tests for complete coverage of path delay faults based on stuck-at tests,” Proc. of ICCD, pp. 446-451, 2006.
[10] P. H. Bardell, W. H. McAnney, and J. Savir, Built-in Test for VLSI: Pseudo-Random Techniques, NewYork: Wiley, 1987.
[11] I. Pomeranz and S. M. Reddy, “3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits,” IEEE Trans. on CAD, vol. 24, no. 7, pp. 1050-1058, 1993.
[12] Y. Huang, I. Pomeranz, S. M. Reddy, and J. Rajski, “Improving the property of at-speed tests,” Proc. of IEEE/ACM Int. Conf. CAD, pp. 459-463, 2000.
[13] H. C. Tsai, K. T. Cheng, and S. Bhawmik, “On improving test quality of scan-based BIST,” IEEE Trans. on CAD, vol. 19, no. 8, pp. 928-938, 2000.
[14] D. Xiang, M. J. Chen, J. G. Sun, and H. Fujiwara, “Improving test effectiveness of scan-based BIST using scan chain partitioning,” IEEE Trans. on CAD, vol. 24, no. 6, pp. 916-927, 2005.
[15] B. Koenemann, “LFSR-coded test patterns for scan designs,” Proc. of ETS, pp. 237-242, 1991.
[16] B. Koenemann, C. Barnhart, B. Keller, T. Snethen, O. Farnsworth, and D. Wheater, “A smart BIST variant with guaranteed encoding,” Proc. of IEEE ATS, pp. 325-330, 2001.
[17] R. Kapur, S. Patil, T. J. Snethen, and T. W. Williams, “A weighted random pattern testgeneration system,” IEEE Trans. on CAD, vol. 15, pp. 1020-1025, 1996.
[18] A. Jas, C. V. Krishna, and N. A. Touba, “Weighted pseudo-random hybrid BIST,” IEEE Trans. on VLSI Systems, vol. 12, no. 12, pp. 1277-1283, 2004.
[19] G. Kiefer and H. J. Wunderlich, “Deterministic BIST with multiple scan chains,” Proc. of IEEE ITC, pp. 1057-1064, 2000.
[20] J. Rajski, N. Tamarapalli, and J. Tyszer, “Automated synthesis of large phase shifters for built-in self-test ,” Proc. of IEEE ITC, pp. 1047-1056, 1998.
[21] J. Rajski, J. Tyszer, and N. Zacharia, “Test data decompression for multiple scan designs with boundary scan,” IEEE Trans. on Computers, vol. 47, no. 11, pp. 1188-1200, 1998.
[22] S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, and B. Courtois, “Build in test for circuits with scan based on reseeding of multiple polynomial linear feedback shift registers,” IEEE Trans. on Computers, vol. 44, no.2, pp. 223-233, 1995.
[23] S. Hellebrand, B. Reed, S. Tarnick, H.J. Wonderlich, “Pattern generation for a deterministic BIST scheme,” Proc. Of IEEE/ ACM Int. Conference on Computer-Aided Design, pp. 84-95, 1995.
[24] C. V. Krishna, A. Jas, and N. Touba, “Archieving high encoding efficiency with partial dynamic LFSR reseeding,” ACM Trans. on Design Automation of Electronic Systems, vol. 9, no. 4, pp. 500-516, 2004.
[25] H. S. Kim, Y. Kim, and S. Kang, “Test decompression mechanism using a variable multiple polynomial LFSR,” IEEE Trans. on VLSI System, vol. 11, no. 4, pp. 687-690, 2003.
[26] A. A. Al-Yamani, S. Mitra, and E. J. McCluskey, “Optimized reseeding by seed ordering and encoding,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 2, pp. 264-270, 2005.
[27] L. Li and K. Chakrabarty, “Test set embedding for deterministic BIST using a configurable introduction network,” IEEE Trans. on Computers, vol. 23, no. 9, pp. 1289-1305, 2003.
[28] D. Xiang, S. Gu, J. Su, and Y. Wu, “A cost-effective scan architecture for scan testing with non-scan test power and test application cost,” Proc. of ACM/IEEE Design Automation Conference, pp. 744-747, 2003.
[29] M. A. Shah and J. H. Patel, “Enhancement of the Illinois scan architecture for use with multiple scan inputs,” Proc. of Int. Annual Symposium on VLSI, pp. 167-172, 2004.
[30] F. Brglez, “On testability of combinational networks,” Proc. of IEEE Int. Symp. on Circuits and Systems, pp. 221-225, 1984.
[31] S. Ohtake, K. Ohtani, and H. Fujiwara, “A method of test generation for path delay faults using stuck-at fault test generation algorithms,” Proc. of DATE, pp. 310-325, 2003.
[32] H. K. Lee and D. S. Ha, “On the generation of test patterns for combinational circuits,” Technical report 12-93, Dept. of Electrical Eng., Virginia Polytechnic Institute and State University.
[33] T. M. Niermann, “W. T. Cheng, and J. H. Patel,” “PROOFS: A fast memory efficient sequential circuit fault simulator,” IEEE Trans. on CAD, vol. 11, no. 2, pp. 198-207, 1992.
[34] M. A. Shah and J. H. Patel, “Enhancement of the Illinois scan architecture for use withmultiple scan inputs,” Proc. of Int. Annual Symposium on VLSI, pp. 167-172, 2004.
[35] N. Oh, R. Kapur, and T. W. Williams, “Fast seed computation for reseeding shift register in test pattern compression,” Proc. of IEEE/ACM Int. Conference on CAD, pp. 76-81, 2002.
[36] H. K. Lee and D. S. Ha, “HOPE: An efficient parallel fault simulator for synchronous sequential circuits,” IEEE Trans. on CAD, vol. 15, no. 9, pp. 1048-1058, 1996.
[37] I. Pomeranz and S. M. Reddy, “A measure of quality for n-detection test sets,” IEEE Trans. on Computers, vol. 53, no. 11, pp. 1497-1503, 2004.
[38] A. Saldanha, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, “Equivalence of robust delay-fault and single stuck-at fault test generation,” Proc. of DAC, pp. 173-176, 1992.
[39] M. H. Schultz, F. Fink, and K. Fuchs, “Parallel pattern fault simulation of path delay faults,” Proc. of DAC, pp. 357-363, 1989.
[40] I. Pomeranz and S. M. Reddy, “An efficient non-enumerative method to estimate path delay fault coverage,” IEEE Trans. on CAD, vol. 13, no. 2, pp. 240-250, 1994.
[41] Dong Xiang, Yang Zhao, Krishnendu Chakrabarty and Hideo Fujiwara, "Compressing test data for deterministic BIST using a reconfigurable scan architecture," Proc. of the 15th IEEE Asian Test Symposium, pp. 299- 304, 2006.
[42] Yang Zhao, Dong Xiang and Krishnendu Chakrabarty, "Reducing test data volume for deterministic BIST via test-point insertion," accepted as poster presentation in 12th IEEE European Test Symposium, 2007.
[43] D. Xiang, K. Li, J. G. Sun, and H. Fujiwara, “Reconfigured scan forest for test application cost, test data volume, and test power reduction,” IEEE Trans. on Computers, vol. 56, no. 4, pp. 557-562, 2007.