片上网络服务质量保障研究
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摘要
片上网络(Network on Chip,NoC)是一种的新型的片上系统(System on Chip,SoC)架构。NoC中提供的服务可主要分为两种基本类型:尽力而为( Best Effort,BE )服务和有保障(Guaranteed,GT)服务。QoS中GT服务又可被细分为硬GT和软GT服务。本文中是基于硬GT服务来建立QoS-NoC系统的。硬GT服务是通过预留贮存资源实现的,可看作是面向连接(Connection-oriented)的方式。硬GT服务通常用电路交换建立连接来为片上网络提供硬GT服务,一旦GT连接被建立,建立的GT链路所占用的资源不能被其他数据服务占用,因此,该链路上不存在竞争,GT服务的性能将会得到保证。然而,对于链路建立失败的数据包,其性能诸如传输时延和吞吐量将很难得到保证。本文在虚通道数目有限的情况下,对QoS-NoC的路由算法和网络结构做了改进,以提高数据包的建链成功率,从而提高网络的整体性能。
本文的主要研究工作如下:
(1)采用SystemC语言搭建了基于消息传递式提供多种服务质量保障的片上网络仿真系统(MSNS-QoS-NoC)。
(2)利用双层子网技术构建dualnet-QoS- NoC系统,以此来改善建链情况,并且有效地降低了数据包延时,增大了吞吐量。
(3)在QoS片上网络系统中采用动态虚通道分配策略,构建DY-QoS-NoC系统,提高建链成功率,减小硅片面积。
(4)结合双层子网技术以及动态虚通道分配策略,构建DY-dualnet-QoS- NoC系统,提升建链成功率,减小硅片面积,且分散数据流量,减小包平均传输延时。
Network-on-chip is a new infrastructure of system-on-chip (NoC). Usually the services in NoC has two types: Best Effort and Guaranteed Services. The guaranteed services of QoS include hard guarantees (Hard GT) and statistical guarantees (Soft GT). In this paper, the QoS-NoC system based on Hard GT is designed, by reserving resources, i.e. Connection-oriented. Using circuit switching to set up the connections is used to offer hard GT. Once a connection is set up, its performance is assured due to no contention exists. But if the connection request is failed, the transmission delay and throughtput can not be assured. In this paper, we improve the network performance by optimizing the routing algorithm and network infrastructure to increase the success probobility of setting connections, while the number of virtual channels are limited. We propose the dualnet-QoS-NoC, DY-QoS-NoC and DY-dualnet-QoS-NoC machanism, and the performances are verified on the QoS-NoC simulators.
The main contributions in this paper are as follows:
(1) Develope a MSNS-QoS-NoC simulator based on SystemC language, which offers multi-levels of hard guaranteed service.
(2) Use dual-subnets infrastructure, i.e. dualnet-QoS-NoC, to improve the success probobility of connection requests, thus effectively decreases the packet delay and increases the throughput of NoC .
(3) Propose the DY-QoS-NoC infrastructure by using dynamic virtual channel allocation strategies in the NoC to improve the success probobility of setting connections and to reduce the chip area.
(4) Designed the DY-dualnet-QoS-NoC machamism by combining dual-subnets infrastructure and dynamiclly virtual channel allocation strategies in the NoC system. The success probobility of setting connections is improved and the chip area is saved, while and the transmission delay is recuded due to the balance of the traffic flows.
本文的主要研究工作如下:
(1)采用SystemC语言搭建了基于消息传递式提供多种服务质量保障的片上网络仿真系统(MSNS-QoS-NoC)。
(2)利用双层子网技术构建dualnet-QoS- NoC系统,以此来改善建链情况,并且有效地降低了数据包延时,增大了吞吐量。
(3)在QoS片上网络系统中采用动态虚通道分配策略,构建DY-QoS-NoC系统,提高建链成功率,减小硅片面积。
(4)结合双层子网技术以及动态虚通道分配策略,构建DY-dualnet-QoS- NoC系统,提升建链成功率,减小硅片面积,且分散数据流量,减小包平均传输延时。
Network-on-chip is a new infrastructure of system-on-chip (NoC). Usually the services in NoC has two types: Best Effort and Guaranteed Services. The guaranteed services of QoS include hard guarantees (Hard GT) and statistical guarantees (Soft GT). In this paper, the QoS-NoC system based on Hard GT is designed, by reserving resources, i.e. Connection-oriented. Using circuit switching to set up the connections is used to offer hard GT. Once a connection is set up, its performance is assured due to no contention exists. But if the connection request is failed, the transmission delay and throughtput can not be assured. In this paper, we improve the network performance by optimizing the routing algorithm and network infrastructure to increase the success probobility of setting connections, while the number of virtual channels are limited. We propose the dualnet-QoS-NoC, DY-QoS-NoC and DY-dualnet-QoS-NoC machanism, and the performances are verified on the QoS-NoC simulators.
The main contributions in this paper are as follows:
(1) Develope a MSNS-QoS-NoC simulator based on SystemC language, which offers multi-levels of hard guaranteed service.
(2) Use dual-subnets infrastructure, i.e. dualnet-QoS-NoC, to improve the success probobility of connection requests, thus effectively decreases the packet delay and increases the throughput of NoC .
(3) Propose the DY-QoS-NoC infrastructure by using dynamic virtual channel allocation strategies in the NoC to improve the success probobility of setting connections and to reduce the chip area.
(4) Designed the DY-dualnet-QoS-NoC machamism by combining dual-subnets infrastructure and dynamiclly virtual channel allocation strategies in the NoC system. The success probobility of setting connections is improved and the chip area is saved, while and the transmission delay is recuded due to the balance of the traffic flows.
引文
[1]王晓袁.片上网络系统模型:[硕士生论文].西安电子科技大学,2008
[2] Axel Jantsch, Hannu Tenhunen. Network on Chip. Kluwer [M] Academic Publishers .2003:6.
[3] A. Hemani et.al. Lowering power consumption in clock by using Globally Asynchronous Locally Synchronous Design style. Proc. of Design Automation Conference, 1999.
[4] A Parasuraman, VA Zeithaml, LL Berry. A Conceptual Model of Service Quality and Its Implications for Future Research. Journal of Marketing, 1985.
[5] E Bolotin, I Cidon, R Ginosar, A Kolodny. QNoC: QoS architecture and design process for network on chip. Journal of Systems Architecture, 2004. 50(2-3), page(s) :105-128.
[6] P Vellanki, N Banerjee, KS Chatha. Quality-of-service and error control techniques for mesh-based network-on-chip architectures . Integration, the VLSI Journal, 2005.
[7] L Benini, G De Micheli. Networks on chips: a new SoC paradigm, Computer, 2002:70-78
[8]李忠琦.片上网络系统网络层设计与研究.中国集成电路,2008.9:38-43
[9] WJ Dally. Performance analysis of k-ary n-cube interconnection networks. Computers(Long Beach, CA), IEEE Transactions, 1990.
[10] F. Karim, A. Nguyen, S. Dey.On-chip Communication Architecture for OC-768 Network Processors. Proceedings of 38th Design Automation Conference, 2001.6:. 678-683.
[11] DE Culler, JP Singh. Parallel. Parallel Computer Architecture : a hardware/software approach. Morgan Kaufmann Publishers. 1999:83-84
[12] J.A.J.Leijten,J.L.Meerbergen,A.H.Timmer,et al.Stream Communication between Real-Time Tasks in a High-Performance Multiprocessor.in Design Automation and Test in Europe(DATE'98), LePalais des Congrés de Paris,France,1998:125-131.
[13] Al-Tawil, K.M., ABD-EL-BARR. A survey and comparison of wormhole routing techniques in mesh networks. IEEE Networks , 1997,11:38-45
[14] Mingche Lai,Zhiying Wang,Lei Gao. A Dynamically-Allocated Virtual Channel Architecture with Congestion Awareness for On-Chip Routers. Design Automation Conference, 2008,45:630-633
[15] Li-Wei Wang. A Virtual Channel Calculation Algorithm for Application Specific on-chip Networks. ICINIS.2010.78:541-544
[16] R IJPKEMA E, GOOSSENS K, RADULESCU A, et al.Trade offs in the design of a router with both guaranteedand best effort services for networks on chip[J]. Computers and Digital Techniques, 2003, 150 (5) : 294-302
[17] L Benini, G De Micheli.“Networks on chips: a new SoC paradigm”, Computer, 2002:70-78
[18] BJERREGAARD T, MAHADEVANA S. Survey of research and practices o f network-on-chip[ J] . ACM Computing Surveys, 2006, 38( 1): 1- 51
[19] E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny. QNoC: QoS architecture and design process for network on chip. J. Systems Architecture, special issue on Networks on Chip, 2004, 50(2-3):105-128
[20] T. Bjerregaard and J. Spars?. A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, IEEE, 2005:1226-1231
[21] M. Millberg, E. Nilsson, R. Thid, A. Jantsch.Guaranteed Bandwidth using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition. IEEE. 2004:890-895
[22] K. Goossens, J. Dielissen, and A. R?adulescu.The AEthereal Network on Chip: Concepts, Architectures, and Implementations. IEEE Design and Test of Computers, 22(5), 2005:414-421
[23] W. Weber, D. Chou, J. Swabrick, and D.wingard. .A quality-of-service mechanism forinterconnection networks in system-on-chips. InProceedings of Design, Automation and Testing inEurope Conference (DATE). 2005:1232–1237.
[24] J. Liang, A. Laffely, S. Srinivasan, and R.Tessier.An architecture and compiler for scalable on-chipcommunication.IEEE Trans. VLSI Syst. 12, 7, 2004: 711–726
[25] K. Goossens, A. Hansson. The aethereal network on chip after ten years: Goals,evolution, lessons, and future. Design Automation Conference (DAC). 2010:306–311
[26] T. Marescaux, H. Corporaal.Introducing the SuperGT Network-on-Chip, SuperGT QoS: more than just GT. DAC 2007, 6 :116-121
[27] T. Bjerregaard, and J. Sparso.A scheduling discipline for latency and bandwidth guarantees inasynchronous network-on-chip.In Proceedings of the11th International Symposium on Advanced Resear. In Asynchronous Circuits and Systems. IEEE, 2005: 34-43.
[28] E. Beigne, F. Clermidy, P. Vivet, A.Clouard, andM. Renaudin.An asynchronous NoC architectureproviding low latency service and its multi-leveldesign framework. In Proceedings of the 11thInternational Symposium on Asynchronous Circuitsand Systems (ASYNC). IEEE, 2005: 54–63.
[29] Xiaowen Wu, Yilang Wu, Ling Wang. QoS Router with Both Soft and Hard Guarantee for Network-on-chip.NORCHIP, 2009: 1– 6.
[30] OSCI. About OSCI [N]. Available at www.systemc.org/about. 2007.
[31] J.Bhasker著,夏宇闻译.SystemC入门.北京航空航天大学出版社, 2008:1-10
[32] OSCI. OSCI Fact Sheet [N]. Available at www.systemc.org/about. 2007
[33] IEEE Computer Society. IEEE Standard SystemC. Language Reference Manual[S]. New York: Institute of Electrical and Electronics Engineers, 2006
[34] A. Jalabert, S. Murali, L. Benini, G. D. Micheli,×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip, Proceedings of the conference on Design, automation and test in Europe. 2004.2:16-20,
[35] S.Murali, G.D.Micheli. SUNMAP: A tool for automatic topology selection and generation for NoCs. In In Proceedings of the 41st Design Automation Conference (DAC). 2004: 914–919
[36] M. Coppola, S. Curaba, M. D. Grammatikakis, G. Maruccia, F. Papariello.OCCN: A Network-on-Chip Modeling and Simulation Framework. Proc. Design, Automation and Test in Europe , 2004:174-179.
[37] OPNET Technologies Inc.,“OPNET Modeler.”http://www.opnet.com.
[38] Steven McCanne, Sally Floyd, Kevin Fall, Kannan Varadhan et al. Network simulator - ns2.http://www-mash.cs.berkeley.edu/ns/, 2000.
[39] Z. Li, X. Ling, J. Hu. MSNS: a Top-Down MPI-Style Hierarchical SimulationFramework for Network-on-Chip. Presented at IEEE International Conference on Communications and Mobile Computing (CMC), Kunming, China, 2009:609-614
[40] T Bjerregaard, S Mahadevan. A survey of research and practices of Network-on-chip. ACM Computing Surveys, 2006.
[41] IEEE, "IEEE 802.3 Layer Management", 1988.
[42] A. Sheibanyrad, A. Greiner, and I. Miro-Panades.Multisynchronous and Fully Asynchronous NoCs for GALS Architectures. Design & Test of Computers, IEEE, vol. 25, 2008:572-580.
[2] Axel Jantsch, Hannu Tenhunen. Network on Chip. Kluwer [M] Academic Publishers .2003:6.
[3] A. Hemani et.al. Lowering power consumption in clock by using Globally Asynchronous Locally Synchronous Design style. Proc. of Design Automation Conference, 1999.
[4] A Parasuraman, VA Zeithaml, LL Berry. A Conceptual Model of Service Quality and Its Implications for Future Research. Journal of Marketing, 1985.
[5] E Bolotin, I Cidon, R Ginosar, A Kolodny. QNoC: QoS architecture and design process for network on chip. Journal of Systems Architecture, 2004. 50(2-3), page(s) :105-128.
[6] P Vellanki, N Banerjee, KS Chatha. Quality-of-service and error control techniques for mesh-based network-on-chip architectures . Integration, the VLSI Journal, 2005.
[7] L Benini, G De Micheli. Networks on chips: a new SoC paradigm, Computer, 2002:70-78
[8]李忠琦.片上网络系统网络层设计与研究.中国集成电路,2008.9:38-43
[9] WJ Dally. Performance analysis of k-ary n-cube interconnection networks. Computers(Long Beach, CA), IEEE Transactions, 1990.
[10] F. Karim, A. Nguyen, S. Dey.On-chip Communication Architecture for OC-768 Network Processors. Proceedings of 38th Design Automation Conference, 2001.6:. 678-683.
[11] DE Culler, JP Singh. Parallel. Parallel Computer Architecture : a hardware/software approach. Morgan Kaufmann Publishers. 1999:83-84
[12] J.A.J.Leijten,J.L.Meerbergen,A.H.Timmer,et al.Stream Communication between Real-Time Tasks in a High-Performance Multiprocessor.in Design Automation and Test in Europe(DATE'98), LePalais des Congrés de Paris,France,1998:125-131.
[13] Al-Tawil, K.M., ABD-EL-BARR. A survey and comparison of wormhole routing techniques in mesh networks. IEEE Networks , 1997,11:38-45
[14] Mingche Lai,Zhiying Wang,Lei Gao. A Dynamically-Allocated Virtual Channel Architecture with Congestion Awareness for On-Chip Routers. Design Automation Conference, 2008,45:630-633
[15] Li-Wei Wang. A Virtual Channel Calculation Algorithm for Application Specific on-chip Networks. ICINIS.2010.78:541-544
[16] R IJPKEMA E, GOOSSENS K, RADULESCU A, et al.Trade offs in the design of a router with both guaranteedand best effort services for networks on chip[J]. Computers and Digital Techniques, 2003, 150 (5) : 294-302
[17] L Benini, G De Micheli.“Networks on chips: a new SoC paradigm”, Computer, 2002:70-78
[18] BJERREGAARD T, MAHADEVANA S. Survey of research and practices o f network-on-chip[ J] . ACM Computing Surveys, 2006, 38( 1): 1- 51
[19] E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny. QNoC: QoS architecture and design process for network on chip. J. Systems Architecture, special issue on Networks on Chip, 2004, 50(2-3):105-128
[20] T. Bjerregaard and J. Spars?. A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, IEEE, 2005:1226-1231
[21] M. Millberg, E. Nilsson, R. Thid, A. Jantsch.Guaranteed Bandwidth using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition. IEEE. 2004:890-895
[22] K. Goossens, J. Dielissen, and A. R?adulescu.The AEthereal Network on Chip: Concepts, Architectures, and Implementations. IEEE Design and Test of Computers, 22(5), 2005:414-421
[23] W. Weber, D. Chou, J. Swabrick, and D.wingard. .A quality-of-service mechanism forinterconnection networks in system-on-chips. InProceedings of Design, Automation and Testing inEurope Conference (DATE). 2005:1232–1237.
[24] J. Liang, A. Laffely, S. Srinivasan, and R.Tessier.An architecture and compiler for scalable on-chipcommunication.IEEE Trans. VLSI Syst. 12, 7, 2004: 711–726
[25] K. Goossens, A. Hansson. The aethereal network on chip after ten years: Goals,evolution, lessons, and future. Design Automation Conference (DAC). 2010:306–311
[26] T. Marescaux, H. Corporaal.Introducing the SuperGT Network-on-Chip, SuperGT QoS: more than just GT. DAC 2007, 6 :116-121
[27] T. Bjerregaard, and J. Sparso.A scheduling discipline for latency and bandwidth guarantees inasynchronous network-on-chip.In Proceedings of the11th International Symposium on Advanced Resear. In Asynchronous Circuits and Systems. IEEE, 2005: 34-43.
[28] E. Beigne, F. Clermidy, P. Vivet, A.Clouard, andM. Renaudin.An asynchronous NoC architectureproviding low latency service and its multi-leveldesign framework. In Proceedings of the 11thInternational Symposium on Asynchronous Circuitsand Systems (ASYNC). IEEE, 2005: 54–63.
[29] Xiaowen Wu, Yilang Wu, Ling Wang. QoS Router with Both Soft and Hard Guarantee for Network-on-chip.NORCHIP, 2009: 1– 6.
[30] OSCI. About OSCI [N]. Available at www.systemc.org/about. 2007.
[31] J.Bhasker著,夏宇闻译.SystemC入门.北京航空航天大学出版社, 2008:1-10
[32] OSCI. OSCI Fact Sheet [N]. Available at www.systemc.org/about. 2007
[33] IEEE Computer Society. IEEE Standard SystemC. Language Reference Manual[S]. New York: Institute of Electrical and Electronics Engineers, 2006
[34] A. Jalabert, S. Murali, L. Benini, G. D. Micheli,×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip, Proceedings of the conference on Design, automation and test in Europe. 2004.2:16-20,
[35] S.Murali, G.D.Micheli. SUNMAP: A tool for automatic topology selection and generation for NoCs. In In Proceedings of the 41st Design Automation Conference (DAC). 2004: 914–919
[36] M. Coppola, S. Curaba, M. D. Grammatikakis, G. Maruccia, F. Papariello.OCCN: A Network-on-Chip Modeling and Simulation Framework. Proc. Design, Automation and Test in Europe , 2004:174-179.
[37] OPNET Technologies Inc.,“OPNET Modeler.”http://www.opnet.com.
[38] Steven McCanne, Sally Floyd, Kevin Fall, Kannan Varadhan et al. Network simulator - ns2.http://www-mash.cs.berkeley.edu/ns/, 2000.
[39] Z. Li, X. Ling, J. Hu. MSNS: a Top-Down MPI-Style Hierarchical SimulationFramework for Network-on-Chip. Presented at IEEE International Conference on Communications and Mobile Computing (CMC), Kunming, China, 2009:609-614
[40] T Bjerregaard, S Mahadevan. A survey of research and practices of Network-on-chip. ACM Computing Surveys, 2006.
[41] IEEE, "IEEE 802.3 Layer Management", 1988.
[42] A. Sheibanyrad, A. Greiner, and I. Miro-Panades.Multisynchronous and Fully Asynchronous NoCs for GALS Architectures. Design & Test of Computers, IEEE, vol. 25, 2008:572-580.