SoC测试中数据压缩与降低功耗方法研究
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摘要
随着系统集成度与加工技术的飞速发展，特别是系统芯片（System-on-a-chip，SoC）的出现，集成电路进入了一个新的发展时期。SoC技术采用IP (Integrated Circuit)核复用的设计方法，将整个系统映射到单个芯片上，既可以缩短开发周期，又可以减小产品体积，提高了系统整体性能，近年来得到了广泛的关注。
与SoC芯片高集成度和复杂度同时出现的，是其测试数据量、测试功耗也随之增加。现有的自动测试设备ATE在存储容量、测试通道数等方面满足不了测试需求，这对SoC测试提出了严峻的挑战，因而有必要对SoC测试资源进行优化，从而减少测试数据，降低测试功耗。
本文从代码的相关性、Huffman编码的特点、扫描链的特点等方面入手，针对上述所提关键问题展开研究。
首先，针对测试数据中无关位较多，可以对无关位根据需要进行适当赋值的特点，考虑无关位填充后代码之间的相互关系，提出了两种基于相容性和反向相容性的测试数据压缩方案，第一种方案针对具有相容性和连续位的数据块进行编码，后一种方案则针对具有相容性和反向相容性的数据块进行编码，实验证明，二者均能很好的提高测试数据压缩率；
其次，针对Huffman编码的特点，提出了一种基于互补对称性的Huffman编码方案，该方案属于统计码编码方案的一种，不同于传统的基于Huffman编码的方案只对具有相容性的数据块进行编码，该方案能同时对具有相容性和反向相容性的数据块进行编码，实验证明，该方案优于同类基于Huffman编码的编码方案；
再次，在分析测试功耗产生原因的基础上，提出了两种低功耗测试方案。基于测试向量重排序的方案将测试功耗问题等效成旅行商（TSP）问题，考虑到蚁群算法容易陷入到局部最优，将遗传算法融入到蚁群算法中，以找到最优的向量顺序，进而降低测试功耗；基于扫描链修改的方法利用对扫描链修改不影响电路逻辑功能的特点，对扫描链的结构进行修改，从而减少数据传递间的跳变次数，降低测试功耗；
最后，提出了一种基于扫描链调整的测试数据压缩和测试功耗协同优化方案。在该方案中，首先划分扫描单元相容组，以找到具有相容性的扫描单元，对划分后的扫描单元组进行重排序、无关位填充、测试向量重排序和扫描切片差分，并将修改后的测试数据重新编码，从而达到降低测试功耗，提高压缩率的目的。
With the swift development of the system integration and processingtechnology, especially emergence of SoC (System-on-a-chip), IC (IntegratedCircuit) has entered a new period of development. Design of SoC mainly adoptsthe technique of reusable IP (Intellectual-property) cores, and maps the wholesystem to a single chip, so it can greatly short the time to mark, reduce the sizeof products and improve the performance of the system. Therefore, it has beenwidely used in many industrial fields in recent years.
With the increase in integration and complexity, the mount of test data andtest power grow rapidly. As poses severe challenges to SoC test, available testresources such as storage capacities and the number of test channels of ATE don’tsatisfy the test requirements, consequently in order to reduce test data and lowertest power, it is necessary for SoC test resources optimization.
By studying the relationship between two code words, characteristics ofHuffman coding and scan chain, this paper has launched a study on the above-mentioned key issues.
Firstly, according to this feature of many don’t care bits of properlyassignment in the test data, two test data compression schemes based on mixed-compatible data block and complementary compatible data block have beenproposed by exploring the relation of codes after don’t care bits assignment. Thefirst scheme encoding compatible and consecutive data blocks, the later schemeencoding compatible and inversely compatible data blocks. Experimental resultsshow that two schemes can efficient improve compression rate.
Secondly, according to Huffman coding characteristic, a test datacompression scheme based on complementary symmetrical Huffman coding hasbeen proposed, this scheme belongs to a statistical coding scheme. Unlike traditional coding based on Huffman coding, which encoding compatible datablocks, this scheme can simultaneously encoding with compatible and inverselycompatible data blocks. Experimental results show that this scheme is superior tosimilar scheme based on Huffman coding.
Thirdly, on the basis of an analysis of the causes of test power, two lowpower test schemes are proposed. The scheme based on test vector reordering seepower test as a traveling salesman problem (TSP). Considering ant colonyalgorithm convergence easily to a local optimum, this paper make geneticalgorithm into ant colony algorithm to find the optimal vector ordering; Thescheme based on scan chain modification changes the architecture of the scanchain, which reduces the switching activities so as to reduce test power.
Finally, a collaborative optimization scheme of test data compression andtest power based on scan chain adjustment is proposed. In this scheme,compatible scan unit is divided into a group, and the divided scan unit group isreordered, by don’t care bits assignment, test vector reordering and scan slicesdifference, modified test data encoding again so as to reduce test power andimprove compression ratio.
与SoC芯片高集成度和复杂度同时出现的，是其测试数据量、测试功耗也随之增加。现有的自动测试设备ATE在存储容量、测试通道数等方面满足不了测试需求，这对SoC测试提出了严峻的挑战，因而有必要对SoC测试资源进行优化，从而减少测试数据，降低测试功耗。
本文从代码的相关性、Huffman编码的特点、扫描链的特点等方面入手，针对上述所提关键问题展开研究。
首先，针对测试数据中无关位较多，可以对无关位根据需要进行适当赋值的特点，考虑无关位填充后代码之间的相互关系，提出了两种基于相容性和反向相容性的测试数据压缩方案，第一种方案针对具有相容性和连续位的数据块进行编码，后一种方案则针对具有相容性和反向相容性的数据块进行编码，实验证明，二者均能很好的提高测试数据压缩率；
其次，针对Huffman编码的特点，提出了一种基于互补对称性的Huffman编码方案，该方案属于统计码编码方案的一种，不同于传统的基于Huffman编码的方案只对具有相容性的数据块进行编码，该方案能同时对具有相容性和反向相容性的数据块进行编码，实验证明，该方案优于同类基于Huffman编码的编码方案；
再次，在分析测试功耗产生原因的基础上，提出了两种低功耗测试方案。基于测试向量重排序的方案将测试功耗问题等效成旅行商（TSP）问题，考虑到蚁群算法容易陷入到局部最优，将遗传算法融入到蚁群算法中，以找到最优的向量顺序，进而降低测试功耗；基于扫描链修改的方法利用对扫描链修改不影响电路逻辑功能的特点，对扫描链的结构进行修改，从而减少数据传递间的跳变次数，降低测试功耗；
最后，提出了一种基于扫描链调整的测试数据压缩和测试功耗协同优化方案。在该方案中，首先划分扫描单元相容组，以找到具有相容性的扫描单元，对划分后的扫描单元组进行重排序、无关位填充、测试向量重排序和扫描切片差分，并将修改后的测试数据重新编码，从而达到降低测试功耗，提高压缩率的目的。
With the swift development of the system integration and processingtechnology, especially emergence of SoC (System-on-a-chip), IC (IntegratedCircuit) has entered a new period of development. Design of SoC mainly adoptsthe technique of reusable IP (Intellectual-property) cores, and maps the wholesystem to a single chip, so it can greatly short the time to mark, reduce the sizeof products and improve the performance of the system. Therefore, it has beenwidely used in many industrial fields in recent years.
With the increase in integration and complexity, the mount of test data andtest power grow rapidly. As poses severe challenges to SoC test, available testresources such as storage capacities and the number of test channels of ATE don’tsatisfy the test requirements, consequently in order to reduce test data and lowertest power, it is necessary for SoC test resources optimization.
By studying the relationship between two code words, characteristics ofHuffman coding and scan chain, this paper has launched a study on the above-mentioned key issues.
Firstly, according to this feature of many don’t care bits of properlyassignment in the test data, two test data compression schemes based on mixed-compatible data block and complementary compatible data block have beenproposed by exploring the relation of codes after don’t care bits assignment. Thefirst scheme encoding compatible and consecutive data blocks, the later schemeencoding compatible and inversely compatible data blocks. Experimental resultsshow that two schemes can efficient improve compression rate.
Secondly, according to Huffman coding characteristic, a test datacompression scheme based on complementary symmetrical Huffman coding hasbeen proposed, this scheme belongs to a statistical coding scheme. Unlike traditional coding based on Huffman coding, which encoding compatible datablocks, this scheme can simultaneously encoding with compatible and inverselycompatible data blocks. Experimental results show that this scheme is superior tosimilar scheme based on Huffman coding.
Thirdly, on the basis of an analysis of the causes of test power, two lowpower test schemes are proposed. The scheme based on test vector reordering seepower test as a traveling salesman problem (TSP). Considering ant colonyalgorithm convergence easily to a local optimum, this paper make geneticalgorithm into ant colony algorithm to find the optimal vector ordering; Thescheme based on scan chain modification changes the architecture of the scanchain, which reduces the switching activities so as to reduce test power.
Finally, a collaborative optimization scheme of test data compression andtest power based on scan chain adjustment is proposed. In this scheme,compatible scan unit is divided into a group, and the divided scan unit group isreordered, by don’t care bits assignment, test vector reordering and scan slicesdifference, modified test data encoding again so as to reduce test power andimprove compression ratio.
引文
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