应用于USB2.0时钟数据恢复的锁相环设计
摘要
USB2.0接口因为其高速和热插拔特性在现代消费类电子接口技术上有着广泛的应用。根据接收的数据恢复数据和时钟,提供给数字系统一个精准的一个低抖动、与工艺无关数据时钟在数据接收部分非常关键。
本文采用锁相环技术实现480MHz时钟综合以及NRZ数据恢复,主要应用于USB2.0接收端设计。其中,设计了整体环路以及各个模块包括鉴相器、电荷泵、低通滤波器、压控振荡器和一些辅助电路。本次设计主要采用TSMC0.18um CMOS工艺,3.3V工作电压。
文章按照电路系统原理、单元电路设计及仿真和系统性能仿真详细介绍了锁相环电路的设计过程。由仿真见诶过得出单环鉴相器不能完成时钟数据恢复;其次,频率综合的应用中比较了两种电荷泵对锁相环系统的影响。全部电路经仿真基本满足设计要求。
In the digital communication and high speed transceiver field, clock and data recovery circuit is widely used. Providing a low jitter, process independent clock to the receiver is a very important part.
This study is trying to design a completely monolithic phase-locked loop (PLL), which is used for usb2.0 clock generation and NRZ data recovery application. The design work is from top level design to all the bottom blocks, including Phase detector, Charge Pump, Low pass filter, VCO and other auxiliary circuits by TSMC 0.18um CMOS process and 3.3V power supply.
The paper describes the PLL system theory, cell circuit design and simulation, and loop simulation. All the simulation results satisfy high speed USB2.0 spec.
本文采用锁相环技术实现480MHz时钟综合以及NRZ数据恢复,主要应用于USB2.0接收端设计。其中,设计了整体环路以及各个模块包括鉴相器、电荷泵、低通滤波器、压控振荡器和一些辅助电路。本次设计主要采用TSMC0.18um CMOS工艺,3.3V工作电压。
文章按照电路系统原理、单元电路设计及仿真和系统性能仿真详细介绍了锁相环电路的设计过程。由仿真见诶过得出单环鉴相器不能完成时钟数据恢复;其次,频率综合的应用中比较了两种电荷泵对锁相环系统的影响。全部电路经仿真基本满足设计要求。
In the digital communication and high speed transceiver field, clock and data recovery circuit is widely used. Providing a low jitter, process independent clock to the receiver is a very important part.
This study is trying to design a completely monolithic phase-locked loop (PLL), which is used for usb2.0 clock generation and NRZ data recovery application. The design work is from top level design to all the bottom blocks, including Phase detector, Charge Pump, Low pass filter, VCO and other auxiliary circuits by TSMC 0.18um CMOS process and 3.3V power supply.
The paper describes the PLL system theory, cell circuit design and simulation, and loop simulation. All the simulation results satisfy high speed USB2.0 spec.
引文
[1] 万天才 频率合成器技术发展动态《微电子学》,2004
[2] http://www.usb.org/press
[3] IWAKAWA S. Overview of USB2.0 specification. NEC Device Technology International 2001(61):38-45
[4] Don Anderson. 精英科技译 USB 系统体系(Universal Serial Bus System Architecture)北京:中国电力出版社 2001-01-01
[5] 杨士中,黎孝纯,宋景光,锁相技术基础,北京,人民邮电出版社 1977
[6] Gardner F. Charge-pump phase-lock loops ieee 1980
[7] 王成儒,李英伟编著,《USB2.0\原理与工程开发》,国防工业出版社,2004.1
[8] 萧世文、宋延清编著,《USB2.0 硬件设计(第二版)》清华大学出版社 2006.10
[9] S.K.Shanmugam , digital and analog communications systems. New York:Wiley&Sons, 1979
[10] John G. Maneatis, low-jitter process-independent DLL and PLL based on self-biased techniques
[11] John G. Maneatis, Jaeha Kim, Iain McClatchie, Jay Maxey and Manjusha Shankaradas, “Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL,” IEEE Journal of Solid-State Circuits, Vol. 38, No. 11, November 2003
[12] Behzad Razvi, Challenges in design of high-speed clock and data recovery circuit IEEE communications magazine august 2002 P94-P100
[13] Charles R.Hogge, a self correcting clock recovery circuit, IEEE Transctions on letter device, Vol.ED-32, No.12, December 1985
[14] Thomas H.Lee,John F. Bulzacchelli, A 155-MHz clock recovery delay- and phase-locked loop, IEEE Journal of solid-state circuit, Vol.27, No.12, December 1992
[15] Behazad Razavi, challenges in the design of high-speed clock and data recovery circuits.
[16] R,Meyer, Analysis and Design of Analog Integrated Circuit, 2nd., Wiley, New York, 1994
[17] 王志功,光纤通信集成电路设计,高等教育出版社,2003
[18] floyd M. Gardner, charge-pump phase-lock loops, IEEE, 1980
[19] Woogeun Rhee, design of high-performance CMOS charge pumps in phase-locked loops, IEEE 1999
[20] A. Waizman, “A delay line loop for frequency synthesis of deskewed clock,” ISSCC Digest of Technical Paper, 1994
[21] C. Olgaard, et al., “Apparatus for reducing power consumption of device controlled by counter and noise due to counter reload” National Semiconductor Corp., Patent #3341
[22] V. Kaenel, D.Aebischer, C. Piguet, and E. Dijkstra, “A 320MHz, 1.5mW at 1.35V CMOS PLL for microprocessor clock generation,” ISSCC Digest of Technical Papers, 1996.
[23] M. Johnson and E. Hudson, “A variable delay line PLL for CPU coprocessor synchronization,” IEEE Journal of Solid-State Circuits, vol.23, pp.1218-1223, Oct. 1988
[24] I. A. Young, J. K. Greason, and K. L. Wong, “A PLL Clock Generator with 5 to 110MHz of Lock Range for Microprocessors,” IEEE Journal of Solid-State Circuits, vo. 27, pp. 1599-1607, Nov. 1992
[25] J. Maneatis, “Low-jitter and Process-Independent DLL and PLL Based on Self-Biased Techniques,” ISSCC Digest of Technical Papers, 1996
[26] Toru Ogawa, Kenji Taniguchi, “a 50% duty cycle correction circuit for PLL output”, IEEE,2002
[27] Joonsuk Lee, Beomsup Kim, a low-noise fast-lock phase-locked loop with adaptive bandwidth control, IEEE Journal of solid-state circuits Vol.35, No.8, August 2000
[28] 何捷,洪志良,闵昊,DVB-T 接收机中频率综合器的研究,复旦大学博士学位论文,2005.4
[29] 王毓银,数字电路逻辑设计(脉冲与数字电路)第三版,高等教育出版社,1999
[30] Mozhgan Mansuri and Chih-Kong Ken Yang, Jitter Optimization Based on Phase-Locked Loop Design Parameters, JSSCC, Vol. 37, No.11, November, 2002
[2] http://www.usb.org/press
[3] IWAKAWA S. Overview of USB2.0 specification. NEC Device Technology International 2001(61):38-45
[4] Don Anderson. 精英科技译 USB 系统体系(Universal Serial Bus System Architecture)北京:中国电力出版社 2001-01-01
[5] 杨士中,黎孝纯,宋景光,锁相技术基础,北京,人民邮电出版社 1977
[6] Gardner F. Charge-pump phase-lock loops ieee 1980
[7] 王成儒,李英伟编著,《USB2.0\原理与工程开发》,国防工业出版社,2004.1
[8] 萧世文、宋延清编著,《USB2.0 硬件设计(第二版)》清华大学出版社 2006.10
[9] S.K.Shanmugam , digital and analog communications systems. New York:Wiley&Sons, 1979
[10] John G. Maneatis, low-jitter process-independent DLL and PLL based on self-biased techniques
[11] John G. Maneatis, Jaeha Kim, Iain McClatchie, Jay Maxey and Manjusha Shankaradas, “Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL,” IEEE Journal of Solid-State Circuits, Vol. 38, No. 11, November 2003
[12] Behzad Razvi, Challenges in design of high-speed clock and data recovery circuit IEEE communications magazine august 2002 P94-P100
[13] Charles R.Hogge, a self correcting clock recovery circuit, IEEE Transctions on letter device, Vol.ED-32, No.12, December 1985
[14] Thomas H.Lee,John F. Bulzacchelli, A 155-MHz clock recovery delay- and phase-locked loop, IEEE Journal of solid-state circuit, Vol.27, No.12, December 1992
[15] Behazad Razavi, challenges in the design of high-speed clock and data recovery circuits.
[16] R,Meyer, Analysis and Design of Analog Integrated Circuit, 2nd., Wiley, New York, 1994
[17] 王志功,光纤通信集成电路设计,高等教育出版社,2003
[18] floyd M. Gardner, charge-pump phase-lock loops, IEEE, 1980
[19] Woogeun Rhee, design of high-performance CMOS charge pumps in phase-locked loops, IEEE 1999
[20] A. Waizman, “A delay line loop for frequency synthesis of deskewed clock,” ISSCC Digest of Technical Paper, 1994
[21] C. Olgaard, et al., “Apparatus for reducing power consumption of device controlled by counter and noise due to counter reload” National Semiconductor Corp., Patent #3341
[22] V. Kaenel, D.Aebischer, C. Piguet, and E. Dijkstra, “A 320MHz, 1.5mW at 1.35V CMOS PLL for microprocessor clock generation,” ISSCC Digest of Technical Papers, 1996.
[23] M. Johnson and E. Hudson, “A variable delay line PLL for CPU coprocessor synchronization,” IEEE Journal of Solid-State Circuits, vol.23, pp.1218-1223, Oct. 1988
[24] I. A. Young, J. K. Greason, and K. L. Wong, “A PLL Clock Generator with 5 to 110MHz of Lock Range for Microprocessors,” IEEE Journal of Solid-State Circuits, vo. 27, pp. 1599-1607, Nov. 1992
[25] J. Maneatis, “Low-jitter and Process-Independent DLL and PLL Based on Self-Biased Techniques,” ISSCC Digest of Technical Papers, 1996
[26] Toru Ogawa, Kenji Taniguchi, “a 50% duty cycle correction circuit for PLL output”, IEEE,2002
[27] Joonsuk Lee, Beomsup Kim, a low-noise fast-lock phase-locked loop with adaptive bandwidth control, IEEE Journal of solid-state circuits Vol.35, No.8, August 2000
[28] 何捷,洪志良,闵昊,DVB-T 接收机中频率综合器的研究,复旦大学博士学位论文,2005.4
[29] 王毓银,数字电路逻辑设计(脉冲与数字电路)第三版,高等教育出版社,1999
[30] Mozhgan Mansuri and Chih-Kong Ken Yang, Jitter Optimization Based on Phase-Locked Loop Design Parameters, JSSCC, Vol. 37, No.11, November, 2002
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