基于IXP2400网络处理器的发包机的设计与实现
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摘要
随着互联网络技术和微电子技术的不断发展,传统的处理器已经不能满足日益增长的网络应用和服务的需求。因此,一种专为处理网络应用和服务而设计的高性能网络处理器应运而生。所以,有必要对网络处理器进行深入地研究和利用,来满足更加丰富的网络应用需求。
利用IXP2400网络处理器的多微引擎并行处理能力,硬件多线程和可移植软件框架等优势,设计和实现了一个发包机系统。该系统主要用于测试和评估网络应用软件和硬件处理大流量数据包的能力和性能。整个发包机软件设计可以分为:数据通道的程序设计和控制通道的程序设计。
数据通道的程序是运行在微引擎里的程序。在数据通道的程序设计中,使用了一种微码汇编语言来编写代码,以提高微引擎的执行效率,利用软件控制微引擎的硬件多线程处理过程。
控制通道的程序则是运行在XScale核上的程序,主要针对发包机硬件设备构建了BSP和用户控制接口,实现了包括Strap模块、Boot Program模块、内存管理模块、系统初始化模块和控制模块在内的一系列用于控制和管理整个系统的模块。
最后使用两种配置不同的主机平台,在Workbench仿真环境下运行了发包机的微引擎代码。结果表明,发包机系统能以2.5Gbps的速率发送数据包,负责发送数据包的微引擎每个线程的执行负荷最高为9.98%,最低为6.20%,平均负荷在7%左右,说明发包机的发送模块和线程仲裁机制效果非常出色。
Along with the development of the network technology and the micro-electronics technology, the traditional processors are not competent for the need of growing network applications and services. Network processor is designed for the network application especially. So, deep research and efficient use of the network processor are necessary to satisfy the network applications.
Using the parallel microprocessors, hardware multithread and portable software framework, a network packet transmitter system is designed and implemented. The transmitter system can be used to test the performance of capability of the software and hardware of the network applications. The design of the transmitter can be divided into two parts: the design of the data path and the design of control path.
Applications designed for data path run on the microengines. Microengine assembly is used to improve the efficiency of the microengine. Software applications are used to control the hardware level parallel processing.
Applications for control path are the software running on the XScale side. The hardware related BSP and user control API are implemented, including Strap module, Boot Program module, memory management module, system initialization module and control module. These modules are used to manage the whole system.
At last, the code of the microengine is executed in Workbench simulator, using two host computers with different hardware platform. The packet transmitter system can send packets at the speed of 2.5Gbps, the execution load of the threads in mircoengine is from 6.20% to 9.98%, and the average execution load is 7%. This percentage indicates that the transmission module and the threads arbitration mechanism work well.
利用IXP2400网络处理器的多微引擎并行处理能力,硬件多线程和可移植软件框架等优势,设计和实现了一个发包机系统。该系统主要用于测试和评估网络应用软件和硬件处理大流量数据包的能力和性能。整个发包机软件设计可以分为:数据通道的程序设计和控制通道的程序设计。
数据通道的程序是运行在微引擎里的程序。在数据通道的程序设计中,使用了一种微码汇编语言来编写代码,以提高微引擎的执行效率,利用软件控制微引擎的硬件多线程处理过程。
控制通道的程序则是运行在XScale核上的程序,主要针对发包机硬件设备构建了BSP和用户控制接口,实现了包括Strap模块、Boot Program模块、内存管理模块、系统初始化模块和控制模块在内的一系列用于控制和管理整个系统的模块。
最后使用两种配置不同的主机平台,在Workbench仿真环境下运行了发包机的微引擎代码。结果表明,发包机系统能以2.5Gbps的速率发送数据包,负责发送数据包的微引擎每个线程的执行负荷最高为9.98%,最低为6.20%,平均负荷在7%左右,说明发包机的发送模块和线程仲裁机制效果非常出色。
Along with the development of the network technology and the micro-electronics technology, the traditional processors are not competent for the need of growing network applications and services. Network processor is designed for the network application especially. So, deep research and efficient use of the network processor are necessary to satisfy the network applications.
Using the parallel microprocessors, hardware multithread and portable software framework, a network packet transmitter system is designed and implemented. The transmitter system can be used to test the performance of capability of the software and hardware of the network applications. The design of the transmitter can be divided into two parts: the design of the data path and the design of control path.
Applications designed for data path run on the microengines. Microengine assembly is used to improve the efficiency of the microengine. Software applications are used to control the hardware level parallel processing.
Applications for control path are the software running on the XScale side. The hardware related BSP and user control API are implemented, including Strap module, Boot Program module, memory management module, system initialization module and control module. These modules are used to manage the whole system.
At last, the code of the microengine is executed in Workbench simulator, using two host computers with different hardware platform. The packet transmitter system can send packets at the speed of 2.5Gbps, the execution load of the threads in mircoengine is from 6.20% to 9.98%, and the average execution load is 7%. This percentage indicates that the transmission module and the threads arbitration mechanism work well.
引文
[1] 潘卫平, 方红波, 曾烈光. 基于网络处理器的 RPR 综合业务接入平台的设计. 光通信技术, 2006, 12(3): 10~13
[2] Govind S, Govindarajan R. Performance modeling and architecture exploration of network processors. in: Quantitative Evaluation of Systems Second Internetional Conference. 2003. 172~184
[3] 陈泽洪, 朱燕平. 基于 DWDM 技术的网络生存性研究. 高性能计算机技术, 2006, 13(19): 45~47
[4] John L. Hennessy, David A. Patterson. 计算机系统结构量化研究方法(第三版). 机械工业出版社, 2003. 213~215
[5] Janian A, Hasan A, Sheth U, Barrett A. IXP2400 network processor package development. in: Electronic Components and Technology proceeding. 2004. 121~123
[6] Xiao Long Dou, Jia Chun Li, Shou Bing Dong. The Research and Implementation of Transplanting the IPtables/Netfilter to an IXP2400 Based Firewall System. in: Embedded Software and Systems proceeding. 2005. 531~535
[7] Ramanurthi V, McCollum J, Ostler C. System level methology for programming CMP based multi-threaded network processor architectures. in: IEEE Computer Society Annual Symposium. 2005. 102~116
[8] Sridhar Laksmanamurthy. Network Processor Performance Analysis Methodology. Intel Technology Journal, 2002, 24(3): 23~25
[9] De Bernardinis F, Fanucci L, Ramacciotti T. A QoS Internet protocol scheduler on the IXP1200 network platform. in: System-on-Chip for Real-Time Applications proceeding. 2003. 394~399
[10] Zhao L, Luo Y, Bhuyan L. Design and implementation of a content-aware switch using a network processor. in: High Performance Interconnects Proceedings 13th Symposium. 2005. 79~85
[11] Kumar S, Gavrilovska A, Schwan K. C-CORE: Using Communication Cores for High Performance Network Services. in: Network Computing and Applications, 4th IEEEInternational Symposium. 2005. 171~178
[12] Ng B. K, Uddin S, Malik Abusin. A Case Study on the Extensibility of Network in: Processor Based Systems. ICAS-ICNS Conference. 2005. 9~13
[13] Sabrina F, Kanhere S. S, Jha S. Implementation and Performance Analysis of a Packet Scheduler on a Programmable Network Processor. in: Local Computer Networks proceeding. 2005. 242~249
[14] Noonan L. Modeling a network processor using object oriented techniques. in: Digital System Design Euromicro Symposium. 2004. 484~490
[15] Cheng Sheng, Zhange Xu. Implementation of 10gigabit packet switching using IXP network processors. in: Communication Technologh Proceedings. 2003. 532~535
[16] IXA Portability Framework Developer’s Manual. Intel Corporation. 2003: 148~169
[17] Wun B, Buhler J, Crowley P. Exploiting coarse-grained parallelism to accelertate protein motif finding with a network processor. in: Parallel Architectures and Compilation Techniques 14th Internetional Conference. 173~184
[18] Zhen Chen, Chuang Lin, Jia Ni. AnitWorm NPU-based Parallel Bloom Filters for TCP/IP Content Processing in Giga-Ethernet LAN. in: Local Computer Networks 30th Anniversary. in: The IEEE Conference. 2005. 748~755
[19] Intel Corporation. Intel IXP2400 Network Processor Programmer’s Reference Manual, 2003. 465~490
[20] Zhang Wang. Internet Qos: Architectures and Mechanisms for Quality of Service. Morgan Kaufmann Publishers, 2001. 187~191
[21] Intel IXP2400 Network Processor Programmer’s Reference Manual. Intel Corporation, 2004. 231~248
[22] Intel Internet Exchange Architecture Portability Framework Developer’s Manual. Intel Coporation, 2003. 231~267
[23] Intel Internet Exchange Architecture Portbility Framework Reference Manual. Intel Coporation, 2004. 456~278
[24] ARM Architecture Reference Manual. ARM Corp, 2000. 367~384
[25] Intel IXP2400 Network Processor Hardware Reference Manual. Intel Corporation. 2003. 34~57
[26] Chen Yan, Liu Naiqi, Zhang Ke. Integrated Access Device (IAD) Solution Using Intel IXP2350 Network Processor. in: Embedded Software and Systems Second International Conference. 2005. 520~522
[27] Intel WAN/LAN Access Switch Example Design for the Intel IXP1200 Network Processor. Intel Corporation, 2002. 28~31
[28] 李洪杰, 张宏科. 基于网络处理器构建核心路由器方案研究. 计算机工程与应用, 2003: 67~69
[29] Grosse E, Laksman Y. N. Network processors applied to IPv4/IPv6 transition. Network IEEE, 2003, 25(18): 35~39
[30] Shah N. Understanding network processors. Department of Electrical Engineering and Computer Sciences. University of California, 2001. 112~131
[31] Manolis Katevenis. Packet Switch Architecture. Crete Press, 2002. 198~201
[32] Jahangir Hasan, Satish Chandra, Vijakumar T. N. Efficient use of memory bandwidth to improve network processor throughput. in: Computer Architecture Proceeding. 30th Annual International Symposium. 2003. 300~311
[33] Scott Karlin, Larry Peterson. An Extensible Router Architecture, Department of Computer Science. Princeton University, 2001. 12~14
[34] Nie XN, Gazsi L, Engel F, Fettweis G. A new network processor architecture for high speed communications. IEEE Computer Society Press, 1999. 231~239
[35] Tammo Spalink, Scott Karlin, Larry Peterson. Building a Robust Software Based Router Using Network Processors. Department of Computer Science, Princeton University, 2003, 23(12): 102~111
[36] Douglas E. Comer. Network System Design using Network Processors. Pearson Prentice Hall, 2002. 231~242
[37] 蒋鲲鹏, 芦东昕, 缪敬. Linux 与 VxWorks 的板级支持包开发的比较与分析. 计算机工程, 2003, 18(2): 165~167
[38] 蔡一兵, 石晶林. 基于 IXP1200 网络处理器的 VxWorks 产品映象设计. 计算机应用研究, 2005, 14(4): 145~148
[39] 乔峰, 林平分. 基于 VxWorks 的 Flash 文件系统. 北京工业大学学报, 2005, 14(23): 67~69
[40] 李立志, 张朝阳, 陈文正. 实时操作系统 VxWorks 设备驱动程序的编写. 计算机工程, 2003, 18(3): 321~322
[41] 李金库, 张德运, 高磊等. VxWorks 下策略路由研究及其原型实现. 计算机工程与应用, 2004, 12(19): 235~264
[42] 谢月江, 张梅. VxWorks 下设备驱动技术研究. 航天控制, 2004, 7(3): 276~289
[43] Douglas. Comer. 网络处理器与网络设计. 机械工业出版社, 2004. 233~235
[44] 施恩, 郑爱蓉, 杨彬等. 关于 IXP2400 网络处理器的多线程编程技术的研究. 计算机应用研究, 2005, 18(14): 201~204
[45] 钟婷, 刘勇, 耿技. 基于 IXP2400 网络处理器的高速包过滤的研究. 计算机应用, 2005, 16(8): 178~181
[46] 王晓华, 闫守孟, 杨志义. 一种面向 IXP2400 的编程模型. 计算机应用研究, 2005, 19(13): 156~158
[47] 张宏科, 苏伟, 武勇. 网络处理器原理与技术. 北京邮电大学出版社, 2004. 12~34
[48] S. Floyd, V. Jacobson. Random Early Detection Gateways for Congestion Avoidance. IEEE/ACM Transaction on Networking, 1993, 21(14): 159~174
[49] Intel Corporation. Microengine C Compiler Language Support Reference Manual, 2003. 23~37
[50] Scott Shenker, Davide D. Clark. A Scheduling Service Model and a Scheduling Architecture for an Integrated Services Packet Network Pre-print. IEEE/ACM Transaction on Networking, 2003. 176~177
[51] 李希鹏, 刘乃安, 宋国栋. 10G 网络处理器驱动软件的设计与实现. 电子技术应用, 2005, 24(8): 163~165
[52] Douglas E. Comer. 用 TCP/IP 进行网际互联. 北京电子出版社, 2001. 123~126
[53] Douglas E. Corner. Internet Working with TCP/IP Vol 2: Design, Implementation, Interals Third Edition. 电子工业出版社, 2001. 122~123
[54] W. Richard Stevens. TCP/IP Illustrated Volume 1: The Protocols. China Machine Press, 2002. 174~186
[55] Stanley B. Lippman. C++ Primer. 人民邮电出版社, 2006. 443~456
[56] Walter Savitch. Absolute C++(影印版). 机械工业出版社, 2006. 154~167
[57] Bjarne Stroustrup. C++程序设计语言(特别版). 高等教育出版社, 2002. 244~251
[2] Govind S, Govindarajan R. Performance modeling and architecture exploration of network processors. in: Quantitative Evaluation of Systems Second Internetional Conference. 2003. 172~184
[3] 陈泽洪, 朱燕平. 基于 DWDM 技术的网络生存性研究. 高性能计算机技术, 2006, 13(19): 45~47
[4] John L. Hennessy, David A. Patterson. 计算机系统结构量化研究方法(第三版). 机械工业出版社, 2003. 213~215
[5] Janian A, Hasan A, Sheth U, Barrett A. IXP2400 network processor package development. in: Electronic Components and Technology proceeding. 2004. 121~123
[6] Xiao Long Dou, Jia Chun Li, Shou Bing Dong. The Research and Implementation of Transplanting the IPtables/Netfilter to an IXP2400 Based Firewall System. in: Embedded Software and Systems proceeding. 2005. 531~535
[7] Ramanurthi V, McCollum J, Ostler C. System level methology for programming CMP based multi-threaded network processor architectures. in: IEEE Computer Society Annual Symposium. 2005. 102~116
[8] Sridhar Laksmanamurthy. Network Processor Performance Analysis Methodology. Intel Technology Journal, 2002, 24(3): 23~25
[9] De Bernardinis F, Fanucci L, Ramacciotti T. A QoS Internet protocol scheduler on the IXP1200 network platform. in: System-on-Chip for Real-Time Applications proceeding. 2003. 394~399
[10] Zhao L, Luo Y, Bhuyan L. Design and implementation of a content-aware switch using a network processor. in: High Performance Interconnects Proceedings 13th Symposium. 2005. 79~85
[11] Kumar S, Gavrilovska A, Schwan K. C-CORE: Using Communication Cores for High Performance Network Services. in: Network Computing and Applications, 4th IEEEInternational Symposium. 2005. 171~178
[12] Ng B. K, Uddin S, Malik Abusin. A Case Study on the Extensibility of Network in: Processor Based Systems. ICAS-ICNS Conference. 2005. 9~13
[13] Sabrina F, Kanhere S. S, Jha S. Implementation and Performance Analysis of a Packet Scheduler on a Programmable Network Processor. in: Local Computer Networks proceeding. 2005. 242~249
[14] Noonan L. Modeling a network processor using object oriented techniques. in: Digital System Design Euromicro Symposium. 2004. 484~490
[15] Cheng Sheng, Zhange Xu. Implementation of 10gigabit packet switching using IXP network processors. in: Communication Technologh Proceedings. 2003. 532~535
[16] IXA Portability Framework Developer’s Manual. Intel Corporation. 2003: 148~169
[17] Wun B, Buhler J, Crowley P. Exploiting coarse-grained parallelism to accelertate protein motif finding with a network processor. in: Parallel Architectures and Compilation Techniques 14th Internetional Conference. 173~184
[18] Zhen Chen, Chuang Lin, Jia Ni. AnitWorm NPU-based Parallel Bloom Filters for TCP/IP Content Processing in Giga-Ethernet LAN. in: Local Computer Networks 30th Anniversary. in: The IEEE Conference. 2005. 748~755
[19] Intel Corporation. Intel IXP2400 Network Processor Programmer’s Reference Manual, 2003. 465~490
[20] Zhang Wang. Internet Qos: Architectures and Mechanisms for Quality of Service. Morgan Kaufmann Publishers, 2001. 187~191
[21] Intel IXP2400 Network Processor Programmer’s Reference Manual. Intel Corporation, 2004. 231~248
[22] Intel Internet Exchange Architecture Portability Framework Developer’s Manual. Intel Coporation, 2003. 231~267
[23] Intel Internet Exchange Architecture Portbility Framework Reference Manual. Intel Coporation, 2004. 456~278
[24] ARM Architecture Reference Manual. ARM Corp, 2000. 367~384
[25] Intel IXP2400 Network Processor Hardware Reference Manual. Intel Corporation. 2003. 34~57
[26] Chen Yan, Liu Naiqi, Zhang Ke. Integrated Access Device (IAD) Solution Using Intel IXP2350 Network Processor. in: Embedded Software and Systems Second International Conference. 2005. 520~522
[27] Intel WAN/LAN Access Switch Example Design for the Intel IXP1200 Network Processor. Intel Corporation, 2002. 28~31
[28] 李洪杰, 张宏科. 基于网络处理器构建核心路由器方案研究. 计算机工程与应用, 2003: 67~69
[29] Grosse E, Laksman Y. N. Network processors applied to IPv4/IPv6 transition. Network IEEE, 2003, 25(18): 35~39
[30] Shah N. Understanding network processors. Department of Electrical Engineering and Computer Sciences. University of California, 2001. 112~131
[31] Manolis Katevenis. Packet Switch Architecture. Crete Press, 2002. 198~201
[32] Jahangir Hasan, Satish Chandra, Vijakumar T. N. Efficient use of memory bandwidth to improve network processor throughput. in: Computer Architecture Proceeding. 30th Annual International Symposium. 2003. 300~311
[33] Scott Karlin, Larry Peterson. An Extensible Router Architecture, Department of Computer Science. Princeton University, 2001. 12~14
[34] Nie XN, Gazsi L, Engel F, Fettweis G. A new network processor architecture for high speed communications. IEEE Computer Society Press, 1999. 231~239
[35] Tammo Spalink, Scott Karlin, Larry Peterson. Building a Robust Software Based Router Using Network Processors. Department of Computer Science, Princeton University, 2003, 23(12): 102~111
[36] Douglas E. Comer. Network System Design using Network Processors. Pearson Prentice Hall, 2002. 231~242
[37] 蒋鲲鹏, 芦东昕, 缪敬. Linux 与 VxWorks 的板级支持包开发的比较与分析. 计算机工程, 2003, 18(2): 165~167
[38] 蔡一兵, 石晶林. 基于 IXP1200 网络处理器的 VxWorks 产品映象设计. 计算机应用研究, 2005, 14(4): 145~148
[39] 乔峰, 林平分. 基于 VxWorks 的 Flash 文件系统. 北京工业大学学报, 2005, 14(23): 67~69
[40] 李立志, 张朝阳, 陈文正. 实时操作系统 VxWorks 设备驱动程序的编写. 计算机工程, 2003, 18(3): 321~322
[41] 李金库, 张德运, 高磊等. VxWorks 下策略路由研究及其原型实现. 计算机工程与应用, 2004, 12(19): 235~264
[42] 谢月江, 张梅. VxWorks 下设备驱动技术研究. 航天控制, 2004, 7(3): 276~289
[43] Douglas. Comer. 网络处理器与网络设计. 机械工业出版社, 2004. 233~235
[44] 施恩, 郑爱蓉, 杨彬等. 关于 IXP2400 网络处理器的多线程编程技术的研究. 计算机应用研究, 2005, 18(14): 201~204
[45] 钟婷, 刘勇, 耿技. 基于 IXP2400 网络处理器的高速包过滤的研究. 计算机应用, 2005, 16(8): 178~181
[46] 王晓华, 闫守孟, 杨志义. 一种面向 IXP2400 的编程模型. 计算机应用研究, 2005, 19(13): 156~158
[47] 张宏科, 苏伟, 武勇. 网络处理器原理与技术. 北京邮电大学出版社, 2004. 12~34
[48] S. Floyd, V. Jacobson. Random Early Detection Gateways for Congestion Avoidance. IEEE/ACM Transaction on Networking, 1993, 21(14): 159~174
[49] Intel Corporation. Microengine C Compiler Language Support Reference Manual, 2003. 23~37
[50] Scott Shenker, Davide D. Clark. A Scheduling Service Model and a Scheduling Architecture for an Integrated Services Packet Network Pre-print. IEEE/ACM Transaction on Networking, 2003. 176~177
[51] 李希鹏, 刘乃安, 宋国栋. 10G 网络处理器驱动软件的设计与实现. 电子技术应用, 2005, 24(8): 163~165
[52] Douglas E. Comer. 用 TCP/IP 进行网际互联. 北京电子出版社, 2001. 123~126
[53] Douglas E. Corner. Internet Working with TCP/IP Vol 2: Design, Implementation, Interals Third Edition. 电子工业出版社, 2001. 122~123
[54] W. Richard Stevens. TCP/IP Illustrated Volume 1: The Protocols. China Machine Press, 2002. 174~186
[55] Stanley B. Lippman. C++ Primer. 人民邮电出版社, 2006. 443~456
[56] Walter Savitch. Absolute C++(影印版). 机械工业出版社, 2006. 154~167
[57] Bjarne Stroustrup. C++程序设计语言(特别版). 高等教育出版社, 2002. 244~251