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闭环电容式微加速度计接口ASIC研究
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摘要
本论文在深入分析闭环加速度计基本原理的基础上,结合本MEMS中心设计加速度计的经验,利用华润上华CSMC 0.5μm DPDM工艺模型参数设计完成了闭环加速度计信号处理电路。
     闭环加速度计信号处理电路主要包含两部分:模拟部分与数字部分。模拟部分包含控制开关电路、驱动电路、前级运算放大器、采样保持电路、相位调节电路、单位增益缓冲器、基准电流源、电容补偿阵列、开关电压转换电路。电容阵列的采用,可以在一定程度上弥补由于工艺偏差造成的差分电容容值偏差。电容补偿阵列在没有加速度敏感部分的条件下,也能够验证整体电路的功能。数字部分包含环形振荡器、分频器、组合逻辑门、非交叠时钟产生电路。通过数字部分产生了8组不同相位的时序控制信号,各时序信号之间未发生时钟交叠。通过数字电路控制开关的导通与关断,加速度系统处于不同状态。数字电路的时钟是2MHz,一个完整的工作周期由32个状态组成。每个周期是由三个相位组成:检测相位,采样相位,力反馈相位。每个周期始于力反馈相位结束处与检测相位的开始处。整体电路性能如下:电路的满量程范围为-3g~+3g,系统灵敏度为0.78V/g,可检测最小加速度信号为30μg。
     本课题还完成了本电路版图的绘制,通过LPE参数提取进一步验证了本电路的功能的实现。
Based on analyzing the principle of the closed-loop accelerometer and combining the experience of the open-loop accelerometer designed by HIT MEMS center, the interface circuits of the closed-loop accelerometer is designed by using the process parameter of CSMC 0.5μm DPDM.
     The circuits composed of two parts. They are analog part and digital part. The analog part includes the switch controlling circuits, driving circuits, operation amplifier, sample/hold circuits, phase modulating circuits, unity gain buffer, current reference source, compensation capacity array, voltage conversion circuit. Compensation capacity array in the absence of acceleration-sensitive condition also verify the whole circuits function. The digital part includes closed loop oscillator, frequency divider, combinational logic circuit, non-overlapping clock generation circuit. By using the digital part, the entire circuit get 8 different phase sequence controlling signal. Each signal don’t occur the overlapping clock. The accelerometer system is placed in several states by digital circuits which control the opening and closing of various switches. The digital circuits operate at a clock frequency of 2MHz. A repetitive cycle includes 32 states. Each cycle includes three phases: Sensing phase, sample phase, and forcing phase. Each cycle starts with the end of the forcing period and beginning of sensing phase. The circuits performance as follow: the full measurement range can be achieved from -3g to +3g, the sensitivity of the system is 0.78V/g, the minimum acceleration detected can be achieved 30μg.And the compensation capacity array could to a certain extent prevent capacity deviation.
     The thesis has completed the layout of the whole circuit, by LPE extracting parameter to verify the function of the circuits.
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