Sigma-Delta ADC中CIC抽取滤波器的设计
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- 英文论文题名：Design of CIC decimation filter of Sigma-Delta ADC
- 论文作者：申艳 ; 孙泉 ; 齐敏 ; 乔东海
- 英文论文作者：SHEN Yan ; SUN Qun ; QI Min ; QIAO Dong-hai ; School of Electronics and Information ; Soochow University ; Institute of Acoustics ; Chinese Aca Ndemy of Sciences
- 年：2016
- 作者机构：苏州大学电子信息学院;中国科学院声学研究所;
- 论文关键词：小面积 ; 低功耗 ; CIC抽取滤波器 ; Sigma-Delta调制器
- 英文论文关键词：Small size ; Low power consumption ; CIC decimation filter ; Sigma-Delta modulator
- 会议召开时间：2016-08-21
- 会议录名称：2016’中国西部声学学术交流会论文集
- 语种：中文
- 分类号：TN713
- 学会代码：SXJS
- 会议名称：2016’中国西部声学学术交流会
- 会议地点：中国四川成都
- 主办单位：中国声学学会微声学分会、中国声学学会物理声学分会、陕西省声学学会、浙江省声学学会、山东省声学学会、上海市声学学会、黑龙江省声学学会、水声技术重点实验室、重庆市声学学会、西安市声学学会、四川省声学学会
- 学会名称：《声学技术》编辑部
- 页数：4
- 文件大小：458k
- 原文格式：D
- 会议级别：全国
摘要
本文在已设计完成Sigma-Delta调制器芯片的基础上,综合考虑了最终Sigma-Delta ADC芯片的面积与功耗,设计了一种适用于该调制器的递归结构CIC抽取滤波器。本文主要包括两个工作:基于MATLAB和FPGA的CIC抽取滤波器的设计和基于虚拟仪器软件Labview的调制器芯片的测试。以测试得到的调制器芯片输出数据作为所设计的CIC抽取滤波器的仿真输入,通过MATLAB对相关数据进行时域与频域的分析,最终实现了抽取率为64倍的递归结构CIC抽取滤波器的设计,并在原有调制器的性能基础上,实现了信噪比(SNR)提高3.1d B、有效位(ENOB)增加0.4位。
The area and power consumption of the final Sigma-Delta ADC chip is comprehensive considered and a suitable Hogenauer CIC decimation filter is designed based on the completely designed Sigma-Delta modulator. This paper mainly contains two parts: The design of CIC decimation filter based on MATLAB and FPGA; the test of modulator chip based on Labview. Output data of modulator is used as the input of CIC decimation filter. A Hogenauer CIC decimation filter with decimation factor of 64 is realized through the time and frequency domain analysis of relevant data by MATLAB. SNR is improved by 3.1d B and ENOB increased by 0.4bit based on the existing modulator.
The area and power consumption of the final Sigma-Delta ADC chip is comprehensive considered and a suitable Hogenauer CIC decimation filter is designed based on the completely designed Sigma-Delta modulator. This paper mainly contains two parts: The design of CIC decimation filter based on MATLAB and FPGA; the test of modulator chip based on Labview. Output data of modulator is used as the input of CIC decimation filter. A Hogenauer CIC decimation filter with decimation factor of 64 is realized through the time and frequency domain analysis of relevant data by MATLAB. SNR is improved by 3.1d B and ENOB increased by 0.4bit based on the existing modulator.
引文
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[2]潘桃莉,谢光忠,周云,等.改进的抽取滤波器设计[J].微处理机,2011(1):7-10.PAN T L,XIE G Z,ZHOU Y.et al.Design of improved Decimation Filter[J].MICROPRO CESSORS,2011(1):7-10.
[3]施亚.MEMS地震检波器中抽取滤波器的设计与FPGA实现[D].苏州大学,2014.SHI Y.Design and Implementation of Decimation Filter for MEMS Geophones on FPGA[D].Soochow University,2014.
[4]万婷婷,孙丽华.级联梳状积分滤波器的原理及FPGA实现[J].微计算机信息,2009;25(62):236-237.WAN T T,SUN L H.The principles and FPGA implementation of Integrator Cascade Comb filter[J].MICROCOMPUTER INFORMATION,2009;25(62):236-237.
[5]尚文明.Sigma-Delta ADC数字抽取滤波器的设计与优化[D],电子科技大学,2013.SHANG W M.The design and optimization of Digital Decimation Filter for Sigma-Delta ADC[D],University of Electronic Science and Technology of China,2013.
[6]施国勇.数字信号处理FPGA电路设计[M].北京:高等教育出版社,2010:79-80.SHI G Y.digital signal processing of circuit design of FPGA[M].Beijing:Higher Education Press,2010:79-80.