印制电路板去耦网络优化设计
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- 英文论文题名：Optimized Design of PCB Decouple Net
- 论文作者：周磊 ; 刘庆想 ; 张健穹 ; 王邦继 ; 李相强
- 英文论文作者：ZHOU Lei ; LIU Qing-xiang ; ZHANG Jian-qiong ; WANG Bang-ji ; LI Xiang-qiang ; College of Physic Science and Technology ; Southwest Jiaotong University
- 年：2014
- 作者机构：西南交通大学物理科学与技术学院;
- 论文关键词：去耦网络 ; 高频阻抗 ; PCB层叠 ; 引线电感
- 英文论文关键词：decouple net ; high frequency impedance ; PCB stack ; lead inductance
- 会议召开时间：2014-07-21
- 会议录名称：2014年全国电磁兼容与防护技术学术会议论文集（上）
- 语种：中文
- 分类号：TN41
- 学会代码：WBXB
- 会议名称：2014年全国电磁兼容与防护技术学术会议
- 会议地点：中国湖南常德
- 主办单位：中国电子学会微波分会、中国工程物理研究院复杂电磁环境科学与技术重点实验室、总装备部电磁兼容及防护技术专业组、天线与微波技术重点实验室
- 学会名称：《微波学报》编辑部
- 页数：4
- 文件大小：1380k
- 原文格式：D
- 会议级别：全国
摘要
论文基于高频阻抗和瞬间能量传递分析印制电路板(PCB)去耦网络,指出常规设计方法不能使得去耦容量最大化和去耦网络自感最小化,未充分利用PCB自身和去耦电容,限制了去耦网络的性能;通过优化PCB层叠设计和直接在焊盘上过孔,增大了去耦网络容量,减小了去耦网络的自感,同时有利于紧凑化布局。仿真结果表明,优化后的去耦网络性能得到提升,PCB的电源完整性(PI)得到满足。
This article analyzed the factors affecting print circuit board(PCB) decouple net's performance based on high frequency impedance and transient energy transfers. It's conclude common design can't maximize decouple capacity nor minimize decouple net's self inductance so as one can't make the best of PCB itself and decouple capacitors, limiting decouple net's performance. By optimizing PCB stack and making vias on pads directly, besides capacity of the decouple net is increased and self inductance is reduced respectively, it's suit for compact designs. The simulation result shows, optimized decouple net's performance was promoted and power integrity(PI) was met.
This article analyzed the factors affecting print circuit board(PCB) decouple net's performance based on high frequency impedance and transient energy transfers. It's conclude common design can't maximize decouple capacity nor minimize decouple net's self inductance so as one can't make the best of PCB itself and decouple capacitors, limiting decouple net's performance. By optimizing PCB stack and making vias on pads directly, besides capacity of the decouple net is increased and self inductance is reduced respectively, it's suit for compact designs. The simulation result shows, optimized decouple net's performance was promoted and power integrity(PI) was met.
引文
[1]王海涛.多层PCB设计中EDA仿真技术[J].微波学报,2008,28(s1):491-494
[2]Fizesan,R.Pitica,D.Power integrity design tips to minimize the effects of mounting inductance of decoupling capacitors[A].Optimization of Electrical and Electronic Equipment(OPTIM)[C].Brasov:IEEE,2012.36-41
[3]Tripathi,J.N.Nagpal,R.K.;Chhabra,N.K.;Malik,R.;Mukherjee,J.;Apte,P.R.Power Integrity analysis and discrete optimization of decoupling capacitors on high speed power planes by particle swarm optimization[A].Quality Electronic Design(ISQED)[C].Santa Clara,CA:IEEE,2013.670–675
[4]Fizesan,R.T.Pitica,D.;Man,L.Power integrity analysis and bypass capacitor selection using FDM on a printed circuit board[A].Electronics Technology[C].Brno:IEEE,2009.1–6
[5]张木水.高速电路电源分配网络设计与电源完整性分析[D].西安:西安电子科技大学,2009
[6]胡翔骏.电路分析[M].第2版,北京:高等教育出版社,2007.301-309
[2]Fizesan,R.Pitica,D.Power integrity design tips to minimize the effects of mounting inductance of decoupling capacitors[A].Optimization of Electrical and Electronic Equipment(OPTIM)[C].Brasov:IEEE,2012.36-41
[3]Tripathi,J.N.Nagpal,R.K.;Chhabra,N.K.;Malik,R.;Mukherjee,J.;Apte,P.R.Power Integrity analysis and discrete optimization of decoupling capacitors on high speed power planes by particle swarm optimization[A].Quality Electronic Design(ISQED)[C].Santa Clara,CA:IEEE,2013.670–675
[4]Fizesan,R.T.Pitica,D.;Man,L.Power integrity analysis and bypass capacitor selection using FDM on a printed circuit board[A].Electronics Technology[C].Brno:IEEE,2009.1–6
[5]张木水.高速电路电源分配网络设计与电源完整性分析[D].西安:西安电子科技大学,2009
[6]胡翔骏.电路分析[M].第2版,北京:高等教育出版社,2007.301-309