基于动态权衡的新型非易失存储器件体系结构研究综述
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摘要
作为现有存储器的潜在替代技术,新型非易失存储器受到了来自学术界和工业界越来越多的关注.目前,制约新型非易失存储器广泛应用的主要问题包括写延迟长、写操作动态功耗高、写寿命有限等.针对这些问题,传统的解决方法是利用计算机体系结构的方法,通过增加层或者调度的方式加以避免或隐藏.但是,这类解决方案往往存在软硬件开销大、无法同时针对不同问题进行优化等问题.近年来,随着对新型非易失存储材料研究的深入,一系列器件自身所包含的动态权衡特性被陆续发现,这也为体系结构研究提供了新的机遇.基于这些器件自身的动态权衡特性,研究人员提出了一系列新的动态非易失存储器优化方案.与传统的优化方案相比,这类新型方案具有额外硬件开销小、可同时针对多个目标进行优化等优点.首先对非易失存储器存在的问题及传统的优化方案进行了概括;然后对非易失存储器件中3个重要的动态权衡关系进行了介绍;在此基础上,对近年来出现的一系列基于非易失存储器动态权衡特性的体系结构优化方案进行梳理;最后,对此类研究的特点进行了总结,并对未来的发展方向进行了展望.
As a promising alternative candidate for DRAM, non-volatile memory(NVM) technique gains increasing interests from both industry and academia. Currently, the main problems that limit the wide utilization of NVM include considerable long latency for write operation, high energy consumption for write operation and limited write endurance. To solve these problems, the traditional solutions are based on computer architecture methods, such as adding extra level or scheduling scheme. Unfortunately, these solutions often suffer from unavoidable high soft/hardware overheads and can hardly optimize the architecture for more than one target at the same time. In recent years, as the improvement of research on non-volatile materials, several dynamical trade-offs lies in the materials are introduced, which also provides new opportunity for computer architecture research. Based on these trade-offs, several novel NVM architectures have been proposed. Compared with the traditional solutions, these proposed architectures have a series of advantages, such as low hardware overhead and the ability of optimizing for multi-targets. In this survey, we firstly introduce the existing problems of NVM and the traditional solutions. Then, we present three important dynamical trade-offs of NVM. After that, we introduce the newly proposed architectures based on these trade-offs. Finally, we make the conclusion for this kind of research work and point out some potential opportunities.
As a promising alternative candidate for DRAM, non-volatile memory(NVM) technique gains increasing interests from both industry and academia. Currently, the main problems that limit the wide utilization of NVM include considerable long latency for write operation, high energy consumption for write operation and limited write endurance. To solve these problems, the traditional solutions are based on computer architecture methods, such as adding extra level or scheduling scheme. Unfortunately, these solutions often suffer from unavoidable high soft/hardware overheads and can hardly optimize the architecture for more than one target at the same time. In recent years, as the improvement of research on non-volatile materials, several dynamical trade-offs lies in the materials are introduced, which also provides new opportunity for computer architecture research. Based on these trade-offs, several novel NVM architectures have been proposed. Compared with the traditional solutions, these proposed architectures have a series of advantages, such as low hardware overhead and the ability of optimizing for multi-targets. In this survey, we firstly introduce the existing problems of NVM and the traditional solutions. Then, we present three important dynamical trade-offs of NVM. After that, we introduce the newly proposed architectures based on these trade-offs. Finally, we make the conclusion for this kind of research work and point out some potential opportunities.
引文
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[2]Qureshi M,Srinivasan V,Rivers J.Scalable high performance main memory system using phase-change memory technology[C]//Proc of the 36th Annual Int Symp on Computer Architecture.New York:ACM,2009:24-33
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[17]Strukov D.Endurance-write speed tradeoffs in nonvolatile memories[J].Applied Physics A,2016,122(4):302-311
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[22]Qiu Keni,Li Qingan,Xue Chun.Write mode aware loop tiling for high performance low power volatile PCM[C]//Proc of the 51st Annual Conf in Design Automation.New York:ACM,2014:106-111
[23]Pan Chen,Xie Mimi,Hu Jingtong,et al.3M-PCM:Exploiting multiple write modes MLC phase change main memory in embedded systems[C]//Proc of Int Conf on Hardware/Software Codesign and System Synthesis.New York:ACM,2014:33-42
[24]Deng Zhaoxia,Zhang Lunkai,Chong F,et al.Herniated Hash tables:Exploiting multi-level phase change memory for in-place data expansion[C]//Proc of the 1st Int Symp on Memory Systems.New York:ACM,2015:247-257
[25]Qureshi M,Franceschini M,Lastrasmontano L,et al.Morphable memory system:A robust architecture for exploiting multi-level phase change memories[C]//Proc of the 37th Annual Int Symp on Computer Architecture.New York:ACM,2010:153-162
[26]Dong Xiangyu,Xie Yuan.AdaMS:Adaptive MLC/SLCphase-change memory design for file storage[C]//Proc of the 16th Asia and South Pacific Design Automation Conf.Piscataway,NJ:IEEE,2011:31-36
[27]Alibart F,Gao Ligang,Strukov D,et al.High-precision tuning of state for memristive devices by adaptable variationtolerant algorithm[J].Nanotechnology,2011,23(7):075201
[28]Liu Xueqing,Patel V,Lukens J,et al.High-quality aluminum-oxide tunnel barriers for scalable,floating-gate random-access memories(FGRAM)[C]//Proc of Int Conf on Memory Technology and Design.Piscataway,NJ:IEEE,2007:235-237
[29]Yu Hung-Chang,Lin Kai-Chun,Tran L,et al.Cycling endurance optimization scheme for 1mb STT-MRAM in 40nm technology[C]//Proc of Int Conf on Solid-State Circuits.Piscataway,NJ:IEEE,2013:224-225
[30]Likharev K.Layered tunnel barriers for nonvolatile memory devices[J].Applied Physics Letters,1998,73(15):2137-2139
[31]Pickett M,Strukov D,Williams S,et al.Switching dynamics in titanium dioxide memristive devices[J].Journal of Applied Physics,2009,106(7):074508
[32]McPherson J,Kim J,Shanware A,et al.Thermochemical description of dielectric breakdown in high dielectric constant materials[J].Applied Physics Letters,2003,82(13):2121-2123
[33]Yang Joshua,Strukov D,Stewart D.Memristive devices for computing[J].Nature Nanotechnology,2013,8(1):13-24
[34]Mott N,Gurney R.Electronic Processes in Ionic Crystals[M].Oxford,UK:Clarendon Press,1940
[35]Zhang Wangyuan,Li Tao.Characterizing and mitigating the impact of process variations on phase change based memory systems[C]//Proc of the 42nd Annual Int Symp on Microarchitecture.New York:ACM,2009:2-13
[36]Jiang Lei,Zhao Bo,Zhang Youtao,et al.Improving write operations in MLC phase change memory[C]//Proc of the18th Int Symp on High Performance Computer Architecture.Piscataway,NJ:IEEE,2012:201-210
[37]Mantegazza D,Ielmini D,Varesi E,et al.Statistical analysis and modeling of programming and retention in PCM arrays[C]//Proc of Int Electron Devices Meeting.Piscataway,NJ:IEEE,2007:311-314
[38]Awasthi M,Shevgoor M,Sudan K,et al.Efficient scrub mechanisms for error-prone emerging memories[C]//Proc of the 18th Int Symp on High Performance Computer Architecture.Piscataway,NJ:IEEE,2012:15-26
[39]Joshi M,Zhang Wangyuan,Li Tao.Mercury:A fast and energy-efficient multi-level cell based phase change memory system[C]//Proc of the 17th Int Symp on High Performance Computer Architecture.Piscataway,NJ:IEEE,2011:345-356
[40]Jung C,Lee E,Min K,et al.Compact verilog:A model of phase-change RAM transient behaviors for multi-level applications[J].Semiconductor Science and Technology,2011,26(10):105018
[41]Kim K,Ahn S.Reliability investigations for manufacturable high density pram[C]//Proc of the 43rd Annual Int Symp on Reliability Physics.Piscataway,NJ:IEEE,2005:157-162
[42]Choi Y,Song I,Park M,et al.A 20nm 1.8v8GB PRAMwith 40mb/s program bandwidth[C]//Proc of the 59th Int Conf on Solid Circuit.Piscataway,NJ:IEEE,2012:46-48
[43]Zebchuk J,Srinivasan V,Qureshi M,et al.A tagless coherence directory[C]//Proc of the 42nd Annual Int Symp on Microarchitecture.New York:ACM,2009:423-434
[44]Zhao Hongzhou,Shriraman A,Dwarkadas S.SPACE:Sharing pattern-based directory coherence for multicore scalability[C]//Proc of the 19th Int Conf on Parallel Architectures and Compilation Techniques.New York:ACM,2010:135-146
[45]Kelm J,Johnson M,Lumettta S,et al.WAYPOINT:Scaling coherence to thousand-core architectures[C]//Proc of the 19th Int Conf on Parallel Architectures and Compilation Techniques.New York:ACM,2010:99-110
[46]Sánchez D,Kozyrakis C.SCD:A scalable coherence directory with flexible sharer set encoding[C]//Proc of the18th Int Symp on High Performance Computer Architecture.Piscataway,NJ:IEEE,2012:129-140
[47]Fang Lei,Liu Peng,Hu Qi,et al.Building expressive,areaefficient coherence directories[C]//Proc of the 22nd Int Conf on Parallel Architectures and Compilation Techniques.New York:ACM,2013:299-308
[48]Sanchez D,Kozyrakis C.The ZCache:Decoupling ways and associativity[C]//Proc of the 43rd Annual Int Symp on Microarchitecture.New York:ACM,2010:187-198
[49]Zhang Lunkai,Strukov D B,Saadeldeen H,et al.SpongeDirectory:Flexible sparse directories utilizing multilevel memristors[C]//Proc of the 23rd Int Conf on Parallel Architectures and Compilation Techniques.New York:ACM,2014:61-74
[50]Ramos L,Gorbatov E,Bianchini R.Page placement in hybrid memory systems[C]//Proc of the 25th Int Conf on Supercomputing.New York:ACM,2011:85-95
[51]Deng Zhaoxia,Zhang Lunkai,Chong F,et al.Memory cocktail therapy:A general learning-based framework to optimize dynamic tradeoffs in NVMs[C]//Proc of the 50th Annual Int Symp on Microarchitecture.New York:ACM,2017:232-244
[52]Zhang Mingzhe,Zhang Lunkai,Liu Zhiyong,et al.Quickand-Dirty:Improving performance of MLC PCM by using temporary short writes[C]//Proc of the 35th Int Conf on Computer Design.Piscataway,NJ:IEEE,2017:585-588
[53]Kang D,Baek S,Mutlu O,et al.Amnesic cache management for non-volatile memory[C]//Proc of the 31st Symp on Mass Storage Systems and Technologies.Piscataway,NJ:IEEE,2015:1-13
[54]Liu Renshuo,Yang Chia-Lin,Wu Wei.Optimizing nand flash-based SSDs via retention relaxation[C]//Proc of the10th Int Conf on File and Storage Technologies.Berkely,CA:USENIX Association,2012:115-126
[55]Liu Renshuo,Shen Deyu,Wang Chengyuan,et al.NVMDuet:Unified working memory and persistent store architecture[C]//Proc of the 19th Int Conf on Architectural Support for Programming Languages and Operating Systems.New York:ACM,2014:455-470
[56]Jung J,Cho S.Memorage:Emerging persistent RAM based malleable main memory and storage architecture[C]//Proc of the 27th Int Conf on Supercomputing.New York:ACM,2013:115-126
[2]Qureshi M,Srinivasan V,Rivers J.Scalable high performance main memory system using phase-change memory technology[C]//Proc of the 36th Annual Int Symp on Computer Architecture.New York:ACM,2009:24-33
[3]Xu Cong,Niu Dimin,Muralimanohar N,et al.Overcoming the challenges of crossbar resistive memory architectures[C]//Proc of the 21st Int Symp on High Performance Computer Architecture.Piscataway,NJ:IEEE,2015:476-488
[4]Hosomi M,Yamagishi H,Yamamoto T,et al.A novel nonvolatile memory with spin torque transfer magnetization switching:Spin-RAM[C]//Proc of Int Electron Devices Meeting.Piscataway,NJ:IEEE,2005:459-462
[5]Nigam A,Munira K,Ghosh A,et al.Model based study on energy and performance optimization for STT-RAM[C/OL]//Proc of the 2nd Non-Volatile Memories Workshop.2011[2013-04-01].http://nvmw.ucsd.edu/2011/
[6]Sparsh M,Vetter J.A survey of software techniques for using non-volatile memories for storage and main memory systems[J].IEEE Transactions on Parallel and Distributed Systems,2016,27(5):1537-1550
[7]Intel Corporation.Intel and Micron produce breakthrough memory technology[EB/OL].[2018-03-03].http://newsroom.intel.com/community/intelnewsroom/blog/2015/07/28/intel-and-micron-produce-breakthrough-memory-technology
[8]Western Digital Corporation.SanDisk and HP launch partnership to create memory-driven computing solutions[EB/OL].[2017-10-12].https://www.sandisk.com/about/media-center/press-releases/2015/sandisk-and-hp-launch-partnership
[9]Western Digital Corporation.3D XPoint SSD pictured,performance and endurance revealed at FMS[EB/OL].[2017-10-12].https://www.sandisk.com/about/media-center/pressreleases/2015/sandisk-and-hp-launch-partnership
[10]Cho S,Lee H.Flip-n-write:A simple deterministic technique to improve PRAM write performance,energy and endurance[C]//Proc of the 42nd Annual Int Symp on Microarchitecture.New York:ACM,2009:347-357
[11]Hay A,Strauss K,Sherwood T,et al.Preventing PCMbanks from seizing too much power[C]//Proc of the 44th Annual Int Symp on Microarchitecture.New York:ACM,2011:186-195
[12]Jiang Lei,Zhang Youtao,Childers B,et al.Fpb:Finegrained power budgeting to improve write throughput of multi-level cell phase change memory[C]//Proc of the 45th Annual Int Symp on Microarchitecture.Piscataway,NJ:IEEE,2012:1-12
[13]Qureshi M,Franceschini M,Lastras-Montano L.Improving read performance of phase change memories via write cancellation and write pausing[C]//Proc of the 16th Int Symp on High Performance Computer Architecture.Piscataway,NJ:IEEE,2010:128-138
[14]Saadeldeen H,Franklin D,Chong F,et al.Memristors for neural branch prediction:A case study in strict latency and write endurance challenges[C]//Proc of the 13th Conf on Computing Frontiers.New York:ACM,2013:251-260
[15]Qureshi M,Karidis J,Franceschini M,et al.Enhancing lifetime and security of PCM-based main memory with startgap wear leveling[C]//Proc of the 42nd Annual Int Symp on Microarchitecture.New York:ACM,2009:14-23
[16]Zhou Ping,Zhao Bo,Zhang Youtao,et al.A durable and energy efficient main memory using phase change memory technology[C]//Proc of the 36th Annual Int Symp on Computer Architecture.New York:ACM,2009:14-23
[17]Strukov D.Endurance-write speed tradeoffs in nonvolatile memories[J].Applied Physics A,2016,122(4):302-311
[18]Li Jing,Wu Chao,Lewis S,et al.A novel reconfigurable sensing scheme for variable level storage in phase change memory[C]//Proc of the 3rd Int Memory Workshop.Piscataway,NJ:IEEE,2011:141-144
[19]Li Qingan,Jiang Lei,Zhang Youtao,et al.Compiler directed write-mode selection for high performance low power volatile PCM[C]//Proc of SIGPLAN/SIGBED Conf on Languages,Compilers and Tools for Embedded Systems.New York:ACM,2013:101-110
[20]Zhang Lunkai,Neely B,Chong F,et al.Mellow writes:Extending lifetime in resistive memories through selective slow write backs[C]//Proc of the 43rd Annual Int Symp on Computer Architecture.Piscataway,NJ:IEEE,2016:519-531
[21]Zhang Mingzhe,Zhang Lunkai,Jiang Lei,et al.Balancing performance and lifetime of MLC PCM by using a region retention monitor[C]//Proc of the 23rd Int Symp on High Performance Computer Architecture.Piscataway,NJ:IEEE,2017:385-396
[22]Qiu Keni,Li Qingan,Xue Chun.Write mode aware loop tiling for high performance low power volatile PCM[C]//Proc of the 51st Annual Conf in Design Automation.New York:ACM,2014:106-111
[23]Pan Chen,Xie Mimi,Hu Jingtong,et al.3M-PCM:Exploiting multiple write modes MLC phase change main memory in embedded systems[C]//Proc of Int Conf on Hardware/Software Codesign and System Synthesis.New York:ACM,2014:33-42
[24]Deng Zhaoxia,Zhang Lunkai,Chong F,et al.Herniated Hash tables:Exploiting multi-level phase change memory for in-place data expansion[C]//Proc of the 1st Int Symp on Memory Systems.New York:ACM,2015:247-257
[25]Qureshi M,Franceschini M,Lastrasmontano L,et al.Morphable memory system:A robust architecture for exploiting multi-level phase change memories[C]//Proc of the 37th Annual Int Symp on Computer Architecture.New York:ACM,2010:153-162
[26]Dong Xiangyu,Xie Yuan.AdaMS:Adaptive MLC/SLCphase-change memory design for file storage[C]//Proc of the 16th Asia and South Pacific Design Automation Conf.Piscataway,NJ:IEEE,2011:31-36
[27]Alibart F,Gao Ligang,Strukov D,et al.High-precision tuning of state for memristive devices by adaptable variationtolerant algorithm[J].Nanotechnology,2011,23(7):075201
[28]Liu Xueqing,Patel V,Lukens J,et al.High-quality aluminum-oxide tunnel barriers for scalable,floating-gate random-access memories(FGRAM)[C]//Proc of Int Conf on Memory Technology and Design.Piscataway,NJ:IEEE,2007:235-237
[29]Yu Hung-Chang,Lin Kai-Chun,Tran L,et al.Cycling endurance optimization scheme for 1mb STT-MRAM in 40nm technology[C]//Proc of Int Conf on Solid-State Circuits.Piscataway,NJ:IEEE,2013:224-225
[30]Likharev K.Layered tunnel barriers for nonvolatile memory devices[J].Applied Physics Letters,1998,73(15):2137-2139
[31]Pickett M,Strukov D,Williams S,et al.Switching dynamics in titanium dioxide memristive devices[J].Journal of Applied Physics,2009,106(7):074508
[32]McPherson J,Kim J,Shanware A,et al.Thermochemical description of dielectric breakdown in high dielectric constant materials[J].Applied Physics Letters,2003,82(13):2121-2123
[33]Yang Joshua,Strukov D,Stewart D.Memristive devices for computing[J].Nature Nanotechnology,2013,8(1):13-24
[34]Mott N,Gurney R.Electronic Processes in Ionic Crystals[M].Oxford,UK:Clarendon Press,1940
[35]Zhang Wangyuan,Li Tao.Characterizing and mitigating the impact of process variations on phase change based memory systems[C]//Proc of the 42nd Annual Int Symp on Microarchitecture.New York:ACM,2009:2-13
[36]Jiang Lei,Zhao Bo,Zhang Youtao,et al.Improving write operations in MLC phase change memory[C]//Proc of the18th Int Symp on High Performance Computer Architecture.Piscataway,NJ:IEEE,2012:201-210
[37]Mantegazza D,Ielmini D,Varesi E,et al.Statistical analysis and modeling of programming and retention in PCM arrays[C]//Proc of Int Electron Devices Meeting.Piscataway,NJ:IEEE,2007:311-314
[38]Awasthi M,Shevgoor M,Sudan K,et al.Efficient scrub mechanisms for error-prone emerging memories[C]//Proc of the 18th Int Symp on High Performance Computer Architecture.Piscataway,NJ:IEEE,2012:15-26
[39]Joshi M,Zhang Wangyuan,Li Tao.Mercury:A fast and energy-efficient multi-level cell based phase change memory system[C]//Proc of the 17th Int Symp on High Performance Computer Architecture.Piscataway,NJ:IEEE,2011:345-356
[40]Jung C,Lee E,Min K,et al.Compact verilog:A model of phase-change RAM transient behaviors for multi-level applications[J].Semiconductor Science and Technology,2011,26(10):105018
[41]Kim K,Ahn S.Reliability investigations for manufacturable high density pram[C]//Proc of the 43rd Annual Int Symp on Reliability Physics.Piscataway,NJ:IEEE,2005:157-162
[42]Choi Y,Song I,Park M,et al.A 20nm 1.8v8GB PRAMwith 40mb/s program bandwidth[C]//Proc of the 59th Int Conf on Solid Circuit.Piscataway,NJ:IEEE,2012:46-48
[43]Zebchuk J,Srinivasan V,Qureshi M,et al.A tagless coherence directory[C]//Proc of the 42nd Annual Int Symp on Microarchitecture.New York:ACM,2009:423-434
[44]Zhao Hongzhou,Shriraman A,Dwarkadas S.SPACE:Sharing pattern-based directory coherence for multicore scalability[C]//Proc of the 19th Int Conf on Parallel Architectures and Compilation Techniques.New York:ACM,2010:135-146
[45]Kelm J,Johnson M,Lumettta S,et al.WAYPOINT:Scaling coherence to thousand-core architectures[C]//Proc of the 19th Int Conf on Parallel Architectures and Compilation Techniques.New York:ACM,2010:99-110
[46]Sánchez D,Kozyrakis C.SCD:A scalable coherence directory with flexible sharer set encoding[C]//Proc of the18th Int Symp on High Performance Computer Architecture.Piscataway,NJ:IEEE,2012:129-140
[47]Fang Lei,Liu Peng,Hu Qi,et al.Building expressive,areaefficient coherence directories[C]//Proc of the 22nd Int Conf on Parallel Architectures and Compilation Techniques.New York:ACM,2013:299-308
[48]Sanchez D,Kozyrakis C.The ZCache:Decoupling ways and associativity[C]//Proc of the 43rd Annual Int Symp on Microarchitecture.New York:ACM,2010:187-198
[49]Zhang Lunkai,Strukov D B,Saadeldeen H,et al.SpongeDirectory:Flexible sparse directories utilizing multilevel memristors[C]//Proc of the 23rd Int Conf on Parallel Architectures and Compilation Techniques.New York:ACM,2014:61-74
[50]Ramos L,Gorbatov E,Bianchini R.Page placement in hybrid memory systems[C]//Proc of the 25th Int Conf on Supercomputing.New York:ACM,2011:85-95
[51]Deng Zhaoxia,Zhang Lunkai,Chong F,et al.Memory cocktail therapy:A general learning-based framework to optimize dynamic tradeoffs in NVMs[C]//Proc of the 50th Annual Int Symp on Microarchitecture.New York:ACM,2017:232-244
[52]Zhang Mingzhe,Zhang Lunkai,Liu Zhiyong,et al.Quickand-Dirty:Improving performance of MLC PCM by using temporary short writes[C]//Proc of the 35th Int Conf on Computer Design.Piscataway,NJ:IEEE,2017:585-588
[53]Kang D,Baek S,Mutlu O,et al.Amnesic cache management for non-volatile memory[C]//Proc of the 31st Symp on Mass Storage Systems and Technologies.Piscataway,NJ:IEEE,2015:1-13
[54]Liu Renshuo,Yang Chia-Lin,Wu Wei.Optimizing nand flash-based SSDs via retention relaxation[C]//Proc of the10th Int Conf on File and Storage Technologies.Berkely,CA:USENIX Association,2012:115-126
[55]Liu Renshuo,Shen Deyu,Wang Chengyuan,et al.NVMDuet:Unified working memory and persistent store architecture[C]//Proc of the 19th Int Conf on Architectural Support for Programming Languages and Operating Systems.New York:ACM,2014:455-470
[56]Jung J,Cho S.Memorage:Emerging persistent RAM based malleable main memory and storage architecture[C]//Proc of the 27th Int Conf on Supercomputing.New York:ACM,2013:115-126