一种结合高分辨率TDC的快速全数字锁相环设计
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摘要
针对时间数字转换器(Time-to-Digital Converter,TDC)的分辨率较低,全数字锁相环(All Digital Phase-Locked Loop,ADPLL)锁定参考信号的时间较长等问题,提出一种在高精度TDC基础上快速实现锁定的全数字锁相环.提出的时间数字转换器运用抽头延迟线法和双通道差分延迟线法提高量化精度,采用对称式层次型结构实现对负时间间隔的量化,设计的相调电路将量化的脉冲信号还原为时间长度信号,通过状态机对反馈信号的相位提前或延迟,实现对参考信号的快速锁定,在环路锁定后使用下降沿检测电路适时关闭鉴频鉴相器和时间数字转换器,降低整体电路的功耗.在Xilinx KC705开发平台上进行仿真与验证,并在Xpower软件上与传统的基于游标尺链型的全数字锁相环进行功耗对比分析.结果表明,此全数字锁相环的量化误差控制在0.2 ns之内,反馈信号可在3个参考信号时钟周期内快速锁定参考信号,整体电路功耗相比传统的基于游标尺链型的全数字锁相环降低约18.1%.本文提出的全数字锁相环具有实时性强、锁定速度快、量化精度高、功耗低等优势,更适用于高速、低功耗的现代数字通信系统.
Aiming at the problems that time-to-digital converter( TDC) suffers a low resolution and all digital phaselocked loop( ADPLL) takes a longer time to lock reference signal,this paper proposes a fast locking ADPLL based on high precision TDC. The new TDC employs tapped delay line method and double-channel differential delay line method to improve quantization accuracy,and uses symmetric hierarchical structure to quantize negative time interval. Meanwhile,the proposed phase modulation circuit recovers quantitative pulse signal into time span signal,and advances or delays phase of feedback signal by state machine to achieve fast locking on reference signal.Moreover,it applys detection circuit of falling edge to turn off phase frequency detector and TDC,which reduce the power consumption of the entire circuit at proper time. Simulation and verification are carried out in the Xilinx KC705 development kit,and contrastive analysis on power consumption is provided between new design and traditional ADPLL based on vernier chain in Xpower software. The results show that quantization error of new ADPLL is restricted within 0.2 ns. Besides,feedback signal can rapidly lock the reference signal in three reference signal clock periods. Power consumption of the overall circuit is cut down by approximately 18. 1% compared to traditional ADPLL based on vernier chain. The proposed ADPLL has the advantages of strong real-time performance,high locking speed,high quantitative precision and low power consumption,and it is more applicable for modern digital communication systems that demand for high speed and low power consumption.
Aiming at the problems that time-to-digital converter( TDC) suffers a low resolution and all digital phaselocked loop( ADPLL) takes a longer time to lock reference signal,this paper proposes a fast locking ADPLL based on high precision TDC. The new TDC employs tapped delay line method and double-channel differential delay line method to improve quantization accuracy,and uses symmetric hierarchical structure to quantize negative time interval. Meanwhile,the proposed phase modulation circuit recovers quantitative pulse signal into time span signal,and advances or delays phase of feedback signal by state machine to achieve fast locking on reference signal.Moreover,it applys detection circuit of falling edge to turn off phase frequency detector and TDC,which reduce the power consumption of the entire circuit at proper time. Simulation and verification are carried out in the Xilinx KC705 development kit,and contrastive analysis on power consumption is provided between new design and traditional ADPLL based on vernier chain in Xpower software. The results show that quantization error of new ADPLL is restricted within 0.2 ns. Besides,feedback signal can rapidly lock the reference signal in three reference signal clock periods. Power consumption of the overall circuit is cut down by approximately 18. 1% compared to traditional ADPLL based on vernier chain. The proposed ADPLL has the advantages of strong real-time performance,high locking speed,high quantitative precision and low power consumption,and it is more applicable for modern digital communication systems that demand for high speed and low power consumption.
引文
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[8]张陆,张长春,李卫,等.应用于全数字锁相环的时间数字转换器设计[J].南京邮电大学学报(自然科学版),2014,34(1):47ZHANG Lu,ZHANG Changchun,LI Wei,et al.Design of Time-toDigital Converter for All Digital Phase-locked Loops[J].Journal of Nanjing University of Posts and Telecommunications,2014,34(1):47
[9]ELKHOLY A,ANAND T,CHOI W S,et al.A 3.7mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC[J].IEEE Journal of Solid-State Circuits,2015,50(4):867
[10]姚亚峰,孙金傲,霍兴华,等.一种结合高精度TDC的快速全数字锁相环[J].湖南大学学报(自然科学版),2017,44(8):131YAO Yafeng,SUN Jinao,HUO Xinghua,et al.A fast all digital phase-locked loop combined with high precision TDC[J].Journal of Hunan University(Natural Science),2017,44(8):131
[11]ZENG C,DEEN M J,PENG H.A low-power gateable vernier ring oscillator time-to-digital converter for biomedical imaging applications[J].IEEE Transactions on Biomedical Circuits&Systems,2016,10(2):445
[12]CHOI Y H,KIM B,SIM J Y,et al.A phase-interpolator-based fractional counter for all-digital fractional-N phase-locked loop[J].IEEE Transactions on Circuits&Systems II Express Briefs,2017,64(3):249
[13]KIM S,HONG S,CHANGC S,et al.A 2 GHz synthesized fractional-N ADPLL with dual-referenced interpolating TDC[J].IEEEJournal of Solid-State Circuits,2016,51(2):391
[14]LIN J M,YANG C Y.A fast-locking all-digital phase-locked loop with dynamic loop bandwidth adjustment[J].IEEE Transactions on Circuits&Systems I:Regular Papers,2015,62(10):2411
[15]CHUNG H,ISHIKURO H,KURODA T.A 10-Bit 80-MS/s decision-select successive approximation TDC in 65 nm CMOS[J].IEEE Journal of Solid-State Circuits,2012,47(5):1232
[2]黎金英,艾欣,邓玉辉.微电网电压不平衡的分层补偿控制策略[J].哈尔滨工业大学学报,2016,48(3):46LI Jinying,AI Xin,DENG Yuhui.Hierarchical control strategy for voltage unbalance compensation in micro-grid[J].Journal of Harbin Institute of Technology,2016,48(3):46
[3]赵金良,杨贵杰,赵品志,等.基于SMO的PMSM磁极位置检测技术[J].哈尔滨工业大学学报,2010,42(1):95ZHAO Jinliang,YANG Guijie,ZHAO Pinzhi,et al.Pole position detection techniques of PMSM based on SMO[J].Journal of Harbin Institute of Technology,2010,42(1):95
[4]何峰,吴乐南.下一代高效导航卫星信号频谱分析与波形优化[J].哈尔滨工业大学学报,2012,44(9):101HEFeng,WU Lenan.Spectral analysis and waveform optimization of signals for future GNSS[J].Journal of Harbin Institute of Technology,2012,44(9):101
[5]赵品志,杨贵杰.基于FPGA的全数字轴角变换算法[J].哈尔滨工业大学学报,2010,42(12):1911ZHAO Pinzhi,YANG Guijie.FPGA-based all-digital resolver-digital conversion algorithm[J].Journal of Harbin Institute of Technology,2010,42(12):1911
[6]马爽,吴志勇,高世杰,等.改进的大气激光通信PPM调制解调系统设计[J].哈尔滨工业大学学报,2016,48(5):105MA Shuang,WU Zhiyong,GAO Shijie,et al.Design of modified atmospheric laser communication PPM modulation-demodulation system[J].Journal of Harbin Institute of Technology,2016,48(5):105
[7]ELKHOLY A,SAXENA S,NANDWANA R K,et al.A 2.0-5.5GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider[J].IEEE Journal of SolidState Circuits,2016,51(8):1771
[8]张陆,张长春,李卫,等.应用于全数字锁相环的时间数字转换器设计[J].南京邮电大学学报(自然科学版),2014,34(1):47ZHANG Lu,ZHANG Changchun,LI Wei,et al.Design of Time-toDigital Converter for All Digital Phase-locked Loops[J].Journal of Nanjing University of Posts and Telecommunications,2014,34(1):47
[9]ELKHOLY A,ANAND T,CHOI W S,et al.A 3.7mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC[J].IEEE Journal of Solid-State Circuits,2015,50(4):867
[10]姚亚峰,孙金傲,霍兴华,等.一种结合高精度TDC的快速全数字锁相环[J].湖南大学学报(自然科学版),2017,44(8):131YAO Yafeng,SUN Jinao,HUO Xinghua,et al.A fast all digital phase-locked loop combined with high precision TDC[J].Journal of Hunan University(Natural Science),2017,44(8):131
[11]ZENG C,DEEN M J,PENG H.A low-power gateable vernier ring oscillator time-to-digital converter for biomedical imaging applications[J].IEEE Transactions on Biomedical Circuits&Systems,2016,10(2):445
[12]CHOI Y H,KIM B,SIM J Y,et al.A phase-interpolator-based fractional counter for all-digital fractional-N phase-locked loop[J].IEEE Transactions on Circuits&Systems II Express Briefs,2017,64(3):249
[13]KIM S,HONG S,CHANGC S,et al.A 2 GHz synthesized fractional-N ADPLL with dual-referenced interpolating TDC[J].IEEEJournal of Solid-State Circuits,2016,51(2):391
[14]LIN J M,YANG C Y.A fast-locking all-digital phase-locked loop with dynamic loop bandwidth adjustment[J].IEEE Transactions on Circuits&Systems I:Regular Papers,2015,62(10):2411
[15]CHUNG H,ISHIKURO H,KURODA T.A 10-Bit 80-MS/s decision-select successive approximation TDC in 65 nm CMOS[J].IEEE Journal of Solid-State Circuits,2012,47(5):1232
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