基于环形振荡器的时间数字转换器前期研究进展
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摘要
随着CMOS工艺的不断发展,时间数字转换器(TDC)的性能不断提升,被广泛应用于医学成像、激光测距、全数字锁相环等领域。基于环形振荡器的时间数字转换器(RO-TDC)具有动态范围大和分辨率高的优点,已成为目前研究热点。介绍了RO-TDC的工作原理,综述了RO-TDC的结构类型和发展现状,总结了RO-TDC的发展趋势。
With the development of CMOS process,the performance of time-to-digital converters(TDC)had been continuously improved.They were widely used in biomedical imaging,laser ranging,all-digital phase-locked loops and other fields.The ring oscillator based time-to-digital converters(RO-TDC)became the focus of current researches because of the advantages of wide dynamic range and high resolution.Firstly,the operational principle of RO-TDCs was introduced,and then the structure types and current status of development of the RO-TDCs were discussed.Finally,the development trend of RO-TDCs was concluded.
With the development of CMOS process,the performance of time-to-digital converters(TDC)had been continuously improved.They were widely used in biomedical imaging,laser ranging,all-digital phase-locked loops and other fields.The ring oscillator based time-to-digital converters(RO-TDC)became the focus of current researches because of the advantages of wide dynamic range and high resolution.Firstly,the operational principle of RO-TDCs was introduced,and then the structure types and current status of development of the RO-TDCs were discussed.Finally,the development trend of RO-TDCs was concluded.
引文
[1]WAHEED K,STASZEWSKI R B,DULGER F,et al.Spurious-free time-to-digital conversion in an ADPLL using short dithering sequences[J].IEEE Trans Circ&Syst I:Regu Pap,2011,58(9):2051-2060.
[2]OH T,VENKATRAM H,MOON U K.A timebased pipelined ADC using both voltage and time domain information[J].IEEE J Sol Sta Circ,2014,49(4):961-971.
[3]HENZLER S.Time-to-digital converters[M].New York:Springer Science&Business Media,2010.
[4]SEO Y H,KIM J S,PARK H J,et al.A 0.63ps resolution,11 b pipeline TDC in 0.13μm CMOS[C]∥Symp VLSI Circ Dig Techn Pap.Kyoto,Japan.2011:152-153
[5]DUDEK P,SZCZEPANSKI S,HATFIELD J V.A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line[J].IEEE J Sol Sta Circ,2000,35(2):240-247.
[6]CAO Y,LEROUX P,STEYAERT M.Radiationtolerant delta-sigma time-to-digital converters[M].New York:Springer,2015.
[7]CHOI K C,LEE S W,LEE B C,et al.A time-todigital converter based on a multiphase reference clock and a binary counter with a novel sampling error corrector[J].IEEE Trans Circ&Syst II:Expr Brief,2012,59(3):143-147.
[8]STRAAYER M Z,PERROTT M H.A multi-path gated ring oscillator TDC with first-order noise shaping[J].IEEE J Sol Sta Circ,2009,44(4):1089-1098.
[9]宗士新.高分辨率数字时间转换器的设计[D].哈尔滨工业大学,2012.
[10]HWANG K D,KIM L S.An area efficient asynchronous gated ring oscillator TDC with minimum GRO stages[C]∥Proceed IEEE Int Symp Circ&Syst.Paris,France.2010:3973-3976.
[11]WU J,CHANG L,LI W,et al.Temperature compensated and gated CMOS ring oscillator for time-todigital converter application[J].Analog Integr Circ&Signal Process,2016,90(3):513-521.
[12]JIANG C,HUANG Y M,HONG Z L.A multi-path gated ring oscillator based time-to-digital converter in65nm CMOS technology[J].J Semicond,2013,34(3):035004-1-035004-5.
[13]ELSHAZLY A,RAO S,YOUNG B,et al.A noiseshaping time-to-digital converter using switched-ring oscillators—analysis,design,and measurement techniques[J].IEEE J Sol Sta Circ,2014,49(5):1184-1197.
[14]ATEF M,El-NOZAHI M,HEGAZI E.A secondorder noise-shaping time-to-digital converter using switched-ring oscillator[C]∥IEEE ISCAS.Lisbon,Portugal.2015:1822-1825.
[15]YU W,KIM K S,CHO S H.A 148fs rms integrated noise 4 MHz bandwidth all-digital second-orderΔΣtime-to-digital converter using gated switched-ring oscillator[C]∥Custom Integr Circ Conf.San Jose,CA,USA.2013:1-4.
[16]谢润,刁盛锡,林福江.一种使用增益校准技术的ΔΣ时间数字转换器[J].微电子学与计算机,2016,33(11):137-141.
[17]LIU S,ZHENG Y.A low-power and highly linear 14-bit parallel sampling TDC with power gating and DEM in 65-nm CMOS[J].IEEE Trans Very Large Scale Integr Syst,2016,24(3):1083-1091.
[18]LU P,LISCIDINI A,ANDREANI P.A 3.6mW,90nm CMOS gated-Vernier time-to-digital converter with an equivalent resolution of 3.2ps[J].IEEE J Sol Sta Circ,2012,47(7):1626-1635.
[19]YU J,DAI F F,JAEGER R C.A 12-bit Vernier ring time-to-digital converter in 0.13μm CMOS technology[J].IEEE J Sol Sta Circ,2010,45(4):830-842.
[20]LU P,W U Y,ANDREANI P.A 2.2-ps twodimensional gated-vernier time-to-digital converter with digital calibration[J].IEEE Trans Circ&Syst II:Expr Bri,2016,63(11):1019-1023.
[21]LU P,LISCIDINI A,ANDREANI P.A 2-D GRO vernier time-to-digital converter with large input range and small latency[J].Analog Integr Circ&Signal Process,2013,76(2):195-206.
[22]YU J,DAI F F.A 3-dimensional Vernier ring time-todigital converter in 0.13μm CMOS[C]∥Custom Integr Circ Conf.San Jose,CA,USA.2010:1-4.
[23]XU W,CHEN X,WU J.An overview of theory and techniques for reducing ring oscillator supply voltage sensitivity in mixed-signal SoC[C]∥Int Conf MEC.Jilin,China.2011:2039-2042.
[2]OH T,VENKATRAM H,MOON U K.A timebased pipelined ADC using both voltage and time domain information[J].IEEE J Sol Sta Circ,2014,49(4):961-971.
[3]HENZLER S.Time-to-digital converters[M].New York:Springer Science&Business Media,2010.
[4]SEO Y H,KIM J S,PARK H J,et al.A 0.63ps resolution,11 b pipeline TDC in 0.13μm CMOS[C]∥Symp VLSI Circ Dig Techn Pap.Kyoto,Japan.2011:152-153
[5]DUDEK P,SZCZEPANSKI S,HATFIELD J V.A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line[J].IEEE J Sol Sta Circ,2000,35(2):240-247.
[6]CAO Y,LEROUX P,STEYAERT M.Radiationtolerant delta-sigma time-to-digital converters[M].New York:Springer,2015.
[7]CHOI K C,LEE S W,LEE B C,et al.A time-todigital converter based on a multiphase reference clock and a binary counter with a novel sampling error corrector[J].IEEE Trans Circ&Syst II:Expr Brief,2012,59(3):143-147.
[8]STRAAYER M Z,PERROTT M H.A multi-path gated ring oscillator TDC with first-order noise shaping[J].IEEE J Sol Sta Circ,2009,44(4):1089-1098.
[9]宗士新.高分辨率数字时间转换器的设计[D].哈尔滨工业大学,2012.
[10]HWANG K D,KIM L S.An area efficient asynchronous gated ring oscillator TDC with minimum GRO stages[C]∥Proceed IEEE Int Symp Circ&Syst.Paris,France.2010:3973-3976.
[11]WU J,CHANG L,LI W,et al.Temperature compensated and gated CMOS ring oscillator for time-todigital converter application[J].Analog Integr Circ&Signal Process,2016,90(3):513-521.
[12]JIANG C,HUANG Y M,HONG Z L.A multi-path gated ring oscillator based time-to-digital converter in65nm CMOS technology[J].J Semicond,2013,34(3):035004-1-035004-5.
[13]ELSHAZLY A,RAO S,YOUNG B,et al.A noiseshaping time-to-digital converter using switched-ring oscillators—analysis,design,and measurement techniques[J].IEEE J Sol Sta Circ,2014,49(5):1184-1197.
[14]ATEF M,El-NOZAHI M,HEGAZI E.A secondorder noise-shaping time-to-digital converter using switched-ring oscillator[C]∥IEEE ISCAS.Lisbon,Portugal.2015:1822-1825.
[15]YU W,KIM K S,CHO S H.A 148fs rms integrated noise 4 MHz bandwidth all-digital second-orderΔΣtime-to-digital converter using gated switched-ring oscillator[C]∥Custom Integr Circ Conf.San Jose,CA,USA.2013:1-4.
[16]谢润,刁盛锡,林福江.一种使用增益校准技术的ΔΣ时间数字转换器[J].微电子学与计算机,2016,33(11):137-141.
[17]LIU S,ZHENG Y.A low-power and highly linear 14-bit parallel sampling TDC with power gating and DEM in 65-nm CMOS[J].IEEE Trans Very Large Scale Integr Syst,2016,24(3):1083-1091.
[18]LU P,LISCIDINI A,ANDREANI P.A 3.6mW,90nm CMOS gated-Vernier time-to-digital converter with an equivalent resolution of 3.2ps[J].IEEE J Sol Sta Circ,2012,47(7):1626-1635.
[19]YU J,DAI F F,JAEGER R C.A 12-bit Vernier ring time-to-digital converter in 0.13μm CMOS technology[J].IEEE J Sol Sta Circ,2010,45(4):830-842.
[20]LU P,W U Y,ANDREANI P.A 2.2-ps twodimensional gated-vernier time-to-digital converter with digital calibration[J].IEEE Trans Circ&Syst II:Expr Bri,2016,63(11):1019-1023.
[21]LU P,LISCIDINI A,ANDREANI P.A 2-D GRO vernier time-to-digital converter with large input range and small latency[J].Analog Integr Circ&Signal Process,2013,76(2):195-206.
[22]YU J,DAI F F.A 3-dimensional Vernier ring time-todigital converter in 0.13μm CMOS[C]∥Custom Integr Circ Conf.San Jose,CA,USA.2010:1-4.
[23]XU W,CHEN X,WU J.An overview of theory and techniques for reducing ring oscillator supply voltage sensitivity in mixed-signal SoC[C]∥Int Conf MEC.Jilin,China.2011:2039-2042.
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