基于时间累加器的二阶ΔΣ时间数字转换器

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英文篇名：A second-order ΔΣ TDC using time accumulator 作者：赵磊 ; 张锋 英文作者：Zhao Lei;Zhang Feng;Institute of Microelectronics of Chinese Academy of Sciences;University of Chinese Academy; 关键词：时间数字转换器 ; 时间累加器 ; 噪声整形 ; 时间域 英文关键词：time-to-digital converter(TDC);;time accumulator;;noise shaping;;time-domain 中文刊名：DZJY 英文刊名：Application of Electronic Technique 机构：中国科学院微电子研究所;中国科学院大学; 出版日期：2017-10-06 出版单位：电子技术应用 年：2017 期：v.43;No.472 基金：国家自然科学基金(61474134) 语种：中文; 页：DZJY201710012 页数：5 CN：10 ISSN：11-2305/TN 分类号：53-57

摘要

提出以一个可获得高的分辨率和宽的信号带宽的二阶ΔΣ时间数字转换器(TDC),TDC基于门控环形振荡器型TDC并结合时间差加法器构成的时间累加器实现了二阶量化噪声整形。采用SMIC 28nm工艺设计,Spectre仿真结果表明,在1 M带宽内噪声底约为-82 d Bps~2/Hz,等效到50 Ms/s奈奎斯特率型TDC的分辨率约为2 ps,功耗取决于输入时间间隔,在测量间隔1ns时功耗约为1.19 mW。受到结构限制,这种类型时间数字转换器输入范围较小。
        A second order ΔΣ Time-to-Digital Converter( TDC) is proposed to achieve high resolution and wide signal bandwidth.The proposed TDC based on gated-ring oscillator( GRO)-based TDC achieves second order quantization noise shaping with a time accumulator using time difference adders. Implemented in SMIC 28 nm CMOS process. Spectre simulation results show the noise floor of the TDC within 1 M bandwidth is about-82 d Bps~2/Hz which corresponds to a 50 Ms/s Nyquist-rate TDC and with 2 ps steps. The TDC power consumption depends on the time difference between input edges, typically about 1. 19 mW for 1 ns interval measurement. Limited by the structure, the input range of this type of TDC is small.

引文

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