基于最小门延迟的时间数字转换器设计
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摘要
设计了一种基于最小门延时的时间数字转换器(TDC),该TDC采用游标延迟链结构。在传统的基础上,利用电压比较器产生一个上升沿陡峭的阶跃信号,作为时间测量的内部传输信号,减少了信号在门延时的翻转时间并且降低了功耗。相位判别采用Arbiter电路,提高了时间判断的准确性。利用半静态双边沿D触发器构成了16进制计数器,扩展了测量时间的动态范围,同时降低了功耗。在TSMC 180 nm工艺,1.8 V电源电压下完成整个设计,仿真结果表明,TDC的分辨率为5.3 ps,动态范围为7.2 ns,功耗为6.5 mW,面积为0.18 mm~2。
A time-to-digital converter(TDC) is designed based on the minimum gate delay, a vernier delay chain structure was adopted in the TDC. On the basis of the traditional structure, a steep rising step signal was generated by a voltage comparator, the signal is used as the internal transfer signal for time measuring, such that the power consumption is reduced and the turnover time of gate delay is decreased. The Arbiter circuit was used as phase discrimination, the time measurement accuracy was improved. The hexadecimal counter was designed by using semi-static double edge-triggered flip-flops, it not only extended the dynamic range of time measuring, but also reduced the power consumption. The TDC is designed in TSMC 180 nm CMOS technology with 1.8 V power supply, the simulation result shows that the resolution is 5.3 ps, dynamic range is 7.2 ns, the average power consumption is 6.5 m W and the area is 0.18 mm~2.
A time-to-digital converter(TDC) is designed based on the minimum gate delay, a vernier delay chain structure was adopted in the TDC. On the basis of the traditional structure, a steep rising step signal was generated by a voltage comparator, the signal is used as the internal transfer signal for time measuring, such that the power consumption is reduced and the turnover time of gate delay is decreased. The Arbiter circuit was used as phase discrimination, the time measurement accuracy was improved. The hexadecimal counter was designed by using semi-static double edge-triggered flip-flops, it not only extended the dynamic range of time measuring, but also reduced the power consumption. The TDC is designed in TSMC 180 nm CMOS technology with 1.8 V power supply, the simulation result shows that the resolution is 5.3 ps, dynamic range is 7.2 ns, the average power consumption is 6.5 m W and the area is 0.18 mm~2.
引文
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[9]王伟民,陈志斌,刘宝华.高精度延时电路在激光测距仪器检测中的应用研究[J].光电子技术,2013,33(4):226-229.
[10]CHENG Z,DEEN J M,PENG H.A low-power gateable vernier ring oscillator time-to-digital converter for biomedical imaging applications[J].IEEE Transactions on Biomedical Circuits&System,2016,10(2):445-454.
[11]IM J S,EO Y H,SUH Y,et al.A 300-MS/s,1.76 psresolution,10-b asynchronous pipelined time-to-digital converter with on-chip digital background calibration in 0.13μm CMOS[J].IEEE Journal of Solid-State Circuits,2013,48(2):516-526.
[12]TANVEER M,NISSINEN I,NISSINEN J,et al.Time-to-digital converter based on analog time expansion for 3D time-offlight cameras[J].Proceedings of SPIE 9022,Imag E Sensors and Image System,2014,9022(1):90220A-90220A-11.
[13]ELSHAZLY A,RAO S,YOUNG B,et al.A noise-shaping time-to-digital converter using switched-ring oscillators analysis,design,and measurement techniques[J].IEEE Journal of Solid-State Circuits,2014,49(5):1184-1197.
[14]高源培,李巍.一种应用于全数字锁相环的时间数字转换器设计[J].复旦学报:自然科学版,2015,54(2):168-174.
[15]纪伟伟.应用于全数字锁相环中的时间数字转发器和计数器的研究与设计[D].上海:复旦大学,2013.
[2]MARKOVIC B,TISA S,VILLA F A,et al.A high-linearity,17 ps precision time-to-digital converter based on a single-stage vernier delay loop fine interpolation[J].IEEE Transaction on Circuits&Systems,2013,60(3):557-569.
[3]JANSSON J P,KOSKINEN V,MANTYNIEMI A,et al.A multichannel high-precision CMOS time-to-digital converter for laser-scanner-based perception systems[J].IEEE Transactions on Instrumentation&Measurement,2012,61(9):2581-2590.
[4]KIM M,LEE H,WOO J K,et al.A low-cost and low-power time-to-digital converter using triple-slope time stretching[J].IEEE Transactions on Circuits&SystemsⅡExpress Briefs,2011,58(3):169-173.
[5]TORRES J,AGUILAR A,MARTOS J,et al.Time-to-digital converter based on FPGA with multiple channel capability[J].IEEE Transactions on Nuclear Science,2014,61(1):107-114.
[6]CHOI K C,LEE S W,LEE B C,et al.A time-to-digital converter based on a multiphase reference clock and a binary counter with a novel sampling error corrector[J].IEEE Transactions on Circuits&SystemsⅡExpress Briefs,2012,59(3):143-147.
[7]田中一.游标型时间数字转换器的研究与设计[D].哈尔滨:哈尔滨工业大学,2012.
[8]宗士新.高分辨率数字时间转换器的设计[D].哈尔滨:哈尔滨工业大学,2012.
[9]王伟民,陈志斌,刘宝华.高精度延时电路在激光测距仪器检测中的应用研究[J].光电子技术,2013,33(4):226-229.
[10]CHENG Z,DEEN J M,PENG H.A low-power gateable vernier ring oscillator time-to-digital converter for biomedical imaging applications[J].IEEE Transactions on Biomedical Circuits&System,2016,10(2):445-454.
[11]IM J S,EO Y H,SUH Y,et al.A 300-MS/s,1.76 psresolution,10-b asynchronous pipelined time-to-digital converter with on-chip digital background calibration in 0.13μm CMOS[J].IEEE Journal of Solid-State Circuits,2013,48(2):516-526.
[12]TANVEER M,NISSINEN I,NISSINEN J,et al.Time-to-digital converter based on analog time expansion for 3D time-offlight cameras[J].Proceedings of SPIE 9022,Imag E Sensors and Image System,2014,9022(1):90220A-90220A-11.
[13]ELSHAZLY A,RAO S,YOUNG B,et al.A noise-shaping time-to-digital converter using switched-ring oscillators analysis,design,and measurement techniques[J].IEEE Journal of Solid-State Circuits,2014,49(5):1184-1197.
[14]高源培,李巍.一种应用于全数字锁相环的时间数字转换器设计[J].复旦学报:自然科学版,2015,54(2):168-174.
[15]纪伟伟.应用于全数字锁相环中的时间数字转发器和计数器的研究与设计[D].上海:复旦大学,2013.
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