40nm节点高深宽比接触孔刻蚀电性能稳定性改善
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摘要
随着工艺节点减小,对高深宽比接触孔形貌和关键尺寸的精准控制变得愈加困难。基于40 nm逻辑器件量产数据,研究了高深宽比接触孔刻蚀工艺参数和刻蚀设备内部耗材的磨损对器件电性能稳定性的影响,并提出了工艺改进方案。通过减小SiO_2厚度,减小接触孔深宽比,从而改善孔内聚合物在孔底部沉积的问题;通过优化刻蚀工艺参数提高SiN/SiO_2刻蚀选择比,保持刻蚀后SiO_2的厚度与改进前工艺相同。测试结果表明,工艺改进后接触孔底部关键尺寸稳定性提升36%,接触电阻稳定性提升20%。通过工艺改进提高了电参数稳定性,对40 nm工艺节点逻辑器件产品良率提升起到了关键作用。
As the process nodes decrease, it becomes more difficult to control the morphology and critical dimensions of the high aspect ratio contact hole accurately. Based on the mass production data of the 40 nm logic devices, the influences of etching process parameters of high aspect ratio contact holes and the consumable parts of the etching equipment on the stability of the device electrical parameters were studied and a process improvement scheme was proposed., The polymer residue in the bottom of the holes was improved by reducing the thickness of SiO_2 and the aspect ratio of the contact holes. The thickness of SiO_2 after etching was the same as the original process by optimizing process parameters to improve the selection ratio of SiN/SiO_2 etching. The test results show that the stability of the critical dimension of the bottom of the contact holes increases by 36% and the stability of the contact resistance increases by 20%. The stability of the electrical parameters is improved by improving the existing process, which plays a key role in improving the yield of 40 nm process node logic devices.
As the process nodes decrease, it becomes more difficult to control the morphology and critical dimensions of the high aspect ratio contact hole accurately. Based on the mass production data of the 40 nm logic devices, the influences of etching process parameters of high aspect ratio contact holes and the consumable parts of the etching equipment on the stability of the device electrical parameters were studied and a process improvement scheme was proposed., The polymer residue in the bottom of the holes was improved by reducing the thickness of SiO_2 and the aspect ratio of the contact holes. The thickness of SiO_2 after etching was the same as the original process by optimizing process parameters to improve the selection ratio of SiN/SiO_2 etching. The test results show that the stability of the critical dimension of the bottom of the contact holes increases by 36% and the stability of the contact resistance increases by 20%. The stability of the electrical parameters is improved by improving the existing process, which plays a key role in improving the yield of 40 nm process node logic devices.
引文
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[2] YUNE H S, AHN Y B, KIM J C, et al. CD uniformity improvement of sub 60 nm contact hole using model based OPC [J]. Proceedings of SPIE, 2008, 7140: 71403E-1-71403E-8.
[3] KIM J H, CHO S W, PARK C J, et al. Angular depen-dences of SiO2 etch rates at different bias voltages in CF4, C2F6, and C4F8, plasmas [J]. Thin Solid Films, 2017, 637:43-48.
[4] BARNOLA S, LAPEYRE C, SERVIN I, et al. Etch adjustment for independent CD control in double patterning [C]//Proceedings of IEEE/SEMI Advanced Semiconductor Manufacturing Conference. Berlin, Germany, 2009: 66-69.
[5] BELLANDI E, SONCINI V. SiO2 etch rate modification by ion implantation [J]. Thin Solid Films, 2012, 524: 75-80.
[6] ASHOK A, PAL P. Growth and etch rate study of low temperature anodic silicon dioxide thin films [J]. The Scientific World Journal, 2014, 2014: 106029-1-106029-9.
[7] SON S N, HONG S J. Quantitative evaluation method for etch sidewall profile of through-silicon vias (TSVs) [J]. ETRI Journal, 2014, 36(4):617-624.
[8] LEE J K, JANG I Y, LEE S H, et al. Mechanism of sidewall necking and bowing in the plasma etching of high aspect-ratio contact holes [J]. Journal of the Electrochemical Society, 2010, 157(3): D142-D146.
[9] KIM J K, LEE S H, CHO S I, et al. Study on contact distortion during high aspect ratio contact SiO2 etching [J]. Journal of Vacuum Science & Technology: A, 2015, 33(2): 021303-1-021303-6.
[10] LEE J Y, KIM S N, KIM D H, et al. Electron shading damage enhancement due to no uniform in-hole etch rate in deep contact-hole process [J]. Surface & Coatings Technology, 2010, 205: S360-S364.
[11] YE J J, EGA G R, THOMPSON S P. High aspect ratio etch yield improvement by a novel polymer dump thickness metrology[C]//Proceedings of the 26th Annual SEMI Advanced Semiconductor Manufacturing Conference. Saratoga Springs, NY, USA, 2015:161-166.
[12] ZHONG Q H, MARTIN R, UPADHYAYA G. Determination of semiconductor chamber operating parameters for the optimization of critical dimension uniformity:US 9466466131[P].2016-10-11.
[13] CHANG Y J, HUNG Y C, KUO C L, et al. Hybrid stamping and laser micromachining process for micro-scale hole drilling [J]. Materials & Manufacturing Processes, 2017, 32(15): 1685-1691.
[14] ZHENG Z, HAO J G, LI G R, et al. Contact CD uniformity and hole circularity improvement in 32/28 nm node: effect of substrate properties and chemical material baking temperature[J]. ECS Transactions, 2014, 60(1):165-171.
[15] REN J, ZHANG H Y, ZHANG Y Y. SiN removal process for poly damage control in memory flash[C]// Proceedings of Semiconductor Technology International Conference. Shanghai, China, 2017: 1-3.
[16] RADJENOVIC B M, RADMILOVIC-RADJENOVIC M D, PETROVIC Z L. Dynamics of the profile charging during SiO2 etching in plasma for high aspect ratio trenches [J]. IEEE Transactions on Plasma Science, 2008, 36(4): 874-875.
[17] JEON M H, MISHRA A K, KANG S K, et al. Characteristics of SiO2 etching by using pulse-time modulation in 60 MHz/2 MHz dual-frequency capacitive coupled plasma [J]. Current Applied Physics, 2013, 13(8):1830-1836.
[18] CHEN W S, GU P Y, TSAI M J. Dependence of 20 nm C/H CD windows on critical process parameters [J]. Proceedings of SPIE, 2010, 7639: 76390Y-1-76390Y-12.
[19] KANG S J, YANG H J, MUN S Y. New gate CD control technology using CF4 plasma treatment following HBr/O2 plasma treatment step in gate etch process using organic BARC [J]. IEEE Transactions on Semiconductor Manufacturing, 2007, 20(2): 150-153.
[20] OHMORI T, KASHIBE M, UNE S, et al. Correlational study between SiN etch rate and plasma impedance in electron cyclotron resonance plasma etcher for advanced process control [J]. IEEE Transactions on Semiconductor Manufacturing, 2015, 28(3):236-240.