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High-Speed Planar GaAs Nanowire Arrays with fmax > 75 GHz by Wafer-Scale Bottom-up Growth
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min.css"/> High-Speed Pla<font color="red">na</font>r G<font color="red">aA</font>s Nanowire Arrays with fmax > 75 GHz by Wafer-Scale Bottom-up Growth - Nano Letters (ACS Publications) name="robots" content="noarchive,nofollow" />name="dc.Title" content="High-Speed Planar GaAs Nanowire Arrays with fmax > 75 GHz by Wafer-Scale Bottom-up Growth" />name="dc.Creator" content="Xin Miao" />name="dc.Creator" content="Kelson Chabak" />name="dc.Creator" content="Chen Zhang" />name="dc.Creator" content="Parsian K. Mohseni" />name="dc.Creator" content="Dennis Walker, Jr." />name="dc.Creator" content="Xiuling Li" />name="dc.Subject" content="Bottom-up; VLS; nanowire; III鈭扸; transistor; VLSI" />name="dc.Description" content="Wafer-scale defect-free planar III鈥揤 nanowire (NW) arrays with 鈭?00% yield and precisely defined positions are realized via a patterned vapor鈥搇iquid鈥搒olid (VLS) growth method. Long and uniform planar GaAs NWs were assembled in perfectly parallel arrays to form double-channel T-gated NW array-based high electron mobility transistors (HEMTs) with DC and RF performance surpassing those for all field-effect transistors (FETs) with VLS NWs, carbon nanotubes (CNTs), or graphene channels in-plane with the substrate. For a planar GaAs NW array-based HEMT with 150 nm gate length and 2 V drain bias, the on/off ratio (ION/IOFF), cutoff frequency (fT), and maximum oscillation frequency (fmax) are 104, 33, and 75 GHz, respectively. By characterizing more than 100 devices on a 1.5 脳 1.5 cm2 chip, we prove chip-level electrical uniformity of the planar NW array-based HEMTs and verify the feasibility of using this bottom-up planar NW technology for post-Si large-scale nanoelectronics." />name="dc.Description" content="" />name="dc.Publisher" content="American Chemical Society" />name="dc.Date" scheme="WTN8601" content="December 22, 2014" />name="dc.Type" content="rapid-communication" />name="dc.Format" content="text/HTML" />name="dc.Identifier" scheme="doi" content="10.1021/nl503596j" />name="dc.Language" content="EN" />name="dc.Coverage" content="world" />name="keywords" content="Bottom-up, VLS, nanowire, III鈭扸, transistor, VLSI" />name="MSSmartTagsPreventParsing" content="true"/> nal article pod">
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Letter

High-Speed Planar GaAs Nanowire Arrays with fmax > 75 GHz by Wafer-Scale Bottom-up Growth

Xin Miao 鈥?/sup>namespace.acs.org/2008/acs" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xml:space="preserve">, Kelson Chabak 鈥?/sup>鈥?/sup>namespace.acs.org/2008/acs" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xml:space="preserve">, Chen Zhang 鈥?/sup>namespace.acs.org/2008/acs" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xml:space="preserve">, Parsian K. Mohseni 鈥?/sup>namespace.acs.org/2008/acs" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xml:space="preserve">, Dennis Walker namespace.acs.org/2008/acs" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xml:space="preserve">, Jr.鈥?/sup>namespace.acs.org/2008/acs" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xml:space="preserve">, and Xiuling Li *鈥?/sup> 鈥?/sup> Microand Nanotechnology Laboratory, Universityof Illinois Urbana鈭扖hampaign, 208 N. Wright Street, Urbana, Illinois 61801, UnitedStates鈥?/sup> AirForce Research Laboratory, Sensors Directorate, 2241 Avionics Circle, Wright-PattersonAir Force Base, Ohio 45433, United StatesNano Lett., 2015, 15 (5), pp 2780–2786DOI: 10.1021/nl503596jPublication Date (Web): December 10, 2014Copyright 漏 2014 American Chemical Society*E-mail: xiuling@illinois.edu.

Abstract

Wafer-scale defect-free planar III鈥揤 nanowire (NW) arrays with 鈭?00% yield and precisely defined positions are realized via a patterned vapor鈥搇iquid鈥搒olid (VLS) growth method. Long and uniform planar GaAs NWs were assembled in perfectly parallel arrays to form double-channel T-gated NW array-based high electron mobility transistors (HEMTs) with DC and RF performance surpassing those for all field-effect transistors (FETs) with VLS NWs, carbon nanotubes (CNTs), or graphene channels in-plane with the substrate. For a planar GaAs NW array-based HEMT with 150 nm gate length and 2 V drain bias, the on/off ratio (ION/IOFF), cutoff frequency (fT), and maximum oscillation frequency (fmax) are 104, 33, and 75 GHz, respectively. By characterizing more than 100 devices on a 1.5 脳 1.5 cm2 chip, we prove chip-level electrical uniformity of the planar NW array-based HEMTs and verify the feasibility of using this bottom-up planar NW technology for post-Si large-scale nanoelectronics.

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