PTL: PRAM translation layer

详细信息    查看全文

• 作者：Gyu Sang Choi^a ; ^{castchoi@ynu.ac.kr}Author Vitae ; Byung-Won On^b ; ^{bwon@snu.ac.kr}Author Vitae ; Kwonhue Choi^a ; ^{gonew@ynu.ac.kr}Author Vitae ; Sungwon Yi^c ; ^{sungyi@etri.re.kr}Author Vitae
• 关键词：PRAM ; PRAM translation layer ; Storage systems ; NAND Flash memory ; Flash translation layer
• 刊名：Microprocessors and Microsystems
• 出版年：2013
• 出版时间：February, 2013
• 年：2013
• 卷：37
• 期：1
• 页码：24-32
• 全文大小：1283 K

文摘

In this paper, we attempt to replace NAND Flash memory with PRAM, while PRAM initially targets replacing NOR Flash memory. To achieve it, we need to handle wear-leveling issue of PRAM since the maximum number of writes in PRAM is only 10⁶. Thus, we have proposed PRAM Translation Layer (PTL) to resolve endurance problem for a PRAM-based storage system. We modified FlashSim to support both PRAM and NAND Flash memory and measured the performance by using real workloads from PC and server.

In our experiment, PRAM shows up to 300 % performance improvement compared to NAND Flash memory. Moreover, our results revealed that the PRAM¡¯s endurance is improved up to 25 % compared to NAND Flash memory due to no erase operation. All these results suggest that PRAM is a viable candidate to replace NAND Flash memory.