A clock synchronization method for EtherCAT master

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• 作者：Xin Chen ^{chentonyxin@163.com}Author Vitae ; Di Li ^{itdili@scut.edu.cn}Author Vitae ; Jiafu Wan ; ^{mejwan@scut.edu.cn} ; ^{jiafuwan_76@163.com}Author Vitae ; Nan Zhou ^{nanchow@qq.com}Author Vitae
• 关键词：EtherCAT ; Clock synchronization ; Packet loss
• 刊名：Microprocessors and Microsystems
• 出版年：2016
• 出版时间：October 2016
• 年：2016
• 卷：46
• 期：part_PB
• 页码：211-218
• 全文大小：2102 K
• 卷排序：46

文摘

EtherCAT has been widely applied in the motion control domain due to its advantages of the fast response speed, low CPU usage and good synchronization performance. Although the built-in distributed clock (DC) synchronization mechanism exhibits strong performance between slaves, the method of clock synchronization between the master and the reference clock is left open for selection by users and there are very few studies in this area. This paper introduces three synchronization modes for EtherCAT and analyzes the reasons for packet loss in free run mode and DC mode. This paper presents a novel method to realize the master clock synchronization with the reference clock. The proposed method can eliminate the settling time which is unusual in other synchronization mechanisms. The method is implemented on Windows with real-time extension and experimental results prove its feasibility.