Performance Comparison of Sigma-delta Modulator Architectures for MEMS Accelerometers Using a Fully-Digital Approach

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• 作者：V. Lima^a ; ^{id5998@alunos.uminho.pt} ; N. Brito^b ; F.S. Alves^b ; J. Cabral^b ; J. Gaspar^c ; L.A. Rocha^a ; ^c
• 关键词：Sigma-delta modulator ; MEMS accelerometer ; FPGA
• 刊名：Procedia Engineering
• 出版年：2016
• 出版时间：2016
• 年：2016
• 卷：168
• 期：Complete
• 页码：814-817
• 全文大小：319 K
• 卷排序：168

文摘

A comparison between different architectures of electromechanical sigma-delta modulators applied to MEMS accelerometers is presented here. Several modulation orders (2nd to 5th) and respective gains can be selected, and controlled in real-time, and sensitivity and noise levels have been measured for demonstration of the system on a SOI (25μm thick active layer) fabricated accelerometer. The fully digital configurable sigma-delta modulator was implemented in a FPGA (Field-programmable gate array), enabling a fine tuning of the gains for each architecture, in a very short time, using automated scripting. All the tests presented here were realized with a sampling frequency of 454kHz, with 15 bits of resolution and a decimation ratio of 454 (bandwidth of 1kHz). Best noise figures (63μg/√Hz), as expected, are achieved for a 5th order implementation.